A 300mm wafer-size CMOS image sensor with in-pixel voltage-gain amplifier and column-level differential readout circuitry

Abstract

Large-format image sensors provide us with a new form of vision in several areas such as astronomy and industry. The sensors commonly comprise thinfilm transistors (TFTs) and photodiodes (PDs) on amorphous silicon. The capabilities of the amorphous silicon sensors, however, are insufficient due to the low carrier mobility of the TFTs. Recently several large-format CCDs [1] and CMOS image sensors [2,3] have been developed on crystal silicon wafers for faster readout speed, reduced image lag, high sensitivity and reduced noise.In this paper, we describe the architecture of a wafer-size CMOS image sensor enabling to enlarge the size of the large-format sensor while maintaining good signal quality. The good signal quality is the key for a low-noise and high-framerate image sensor. For this purpose, each pixel of our sensor has a programmable voltage amplifier. In addition, the differential readout circuitry on the column signal path ensures tolerance to common-mode noise and the drift of power/ground voltage.A 202×205mm 2 , 1.6Mpixel, 100 frame-per-second (fps) CMOS image sensor is fabricated on a 300mm wafer in 0.25μm 1P3M CMOS. The diagonal of the sensor is 1.5× larger than that of the conventional wafer-size imager on a 200mm wafer. Figure 23.5.1 shows a conceptual view of the sensor. The chip is formed by stitching 3 fragments named block A, B and C because the area of the chip is larger than the maximum field of view of existing steppers. Stitching one block of A, nineteen blocks of B and one block of C yields one subarray. The subarray includes pixels of 128 columns × 1248 rows, a pair of output buffers for reset and integrated signals, a horizontal scanning circuit (HSC), and a vertical scanning circuit (VSC). Ten subarrays compose the wafer-size image sensor. The VSC is embedded in the array of pixels, therefore the pixel pitch between adjacent pixels at the border of subarrays is the same as that in the subarray. In addition, the sensor can be arranged to 2-by-N tiles to form larger image area because there is no margin both on the edge of block A and on the long sides of the subarray. Figure 23.5.2 shows the layout concept of a pixel array. In the array, a row is flipped horizontally onto its adjacent rows, which yields a space between every 2 rows. Unit cells of both the VSC and the HSC are placed at the spaces between rows. Repeaters are inserted between unit cells of the VSC to regenerate a vertical shift pulse. The body of the PD is fully depleted, and connected with a conductor at its center.Figure 23.5.3 is a schematic view of the signal path from a PD to output terminals. A unit pixel consists of a PD, a source follower (SF), a programmable inpixel voltage amplifier (PGA), and 2 S/H amplifiers for reset and integrated signals. Figure 23.5.4 describes its operation as follows: (1) signal integration, (2) holding an integrated signal at the S/H A, (3) resetting the PGA, (4) resetting the PD while resetting the PGA, and (5) holding the reset signal. All pixels are stimulated at the same time, achieving ...

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