A 300-MHz 64-b quad-issue CMOS RISC microprocessor

Benschneider, B.J.; Black, Andrew J.; Bowhill, William J.; Britton, Sharon M.; Dever, D.E.; Donchin, D.R.; Dupcak, R.; Fromm, Richard; Gowan, M.K.; Gronowski, P.E.; Kantrowitz, M.; Lamere, Marc E.; Mehta, Shekhar; Meyer, J.; Mueller, R.O.; Olesin, A.; Preston, R.P.; Priore, Donald A.; Santhanam, S.; Smith, M.J.; Wolrich, G.M.

doi:10.1109/4.475708

Cited by 53 publications

(6 citation statements)

References 3 publications

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“…The Alpha microprocessors have been implemented with a wide range of circuit styles including conventional complementary CMOS logic, single-and dualrail dynamic logic, cascode logic pass transistor logic, and ratioed static logic [7].…”

Section: Circuit Designmentioning

confidence: 99%

High-performance microprocessor design

Gronowski

Bowhill

Preston

et al. 1998

IEEE J. Solid-State Circuits

Self Cite

251

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Three generations of Alpha microprocessors have been designed using a proven custom design methodology. The performance of these microprocessors was optimized by focusing on high-frequency design. The Alpha instruction set architecture facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths. Digital has developed six generations of CMOS technology optimized for high-frequency design. Complex circuit styles were used extensively to meet aggressive cycle time goals. CAD tools were developed internally to support these designs. This paper discusses some of the technologies that have enabled Alpha microprocessors to achieve high performance.Index Terms-Alpha, CMOS digital integrated circuits, computer architecture, flip-flops, integrated circuit design, logic design, microprocessors.

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Section: Circuit Designmentioning

confidence: 99%

High-performance microprocessor design

Gronowski

Bowhill

Preston

et al. 1998

IEEE J. Solid-State Circuits

Self Cite

251

View full text Add to dashboard Cite

show abstract

“…Manufacturing process technology advancements, architectural innovations, and full-custom circuit design techniques have been significant contributors to Digital's delivery of two additional generations of performance leadership Alpha microprocessors [2,3]. Between the first generation Alpha 21064 and the third generation Alpha 21264 designs, device counts have grown by a factor of 9, from 1.68 million to 15.2 million, while clock frequencies have increased from 200 MHz to 600 MHz, or a factor of 3.…”

Section: Introductionmentioning

confidence: 98%

Power considerations in the design of the Alpha 21264 microprocessor

Gowan¹,

Biro²,

Jackson³

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

293

142

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Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz. This paper describes some of the techniques the Alpha design team utilized to help manage power dissipation. In addition, the electrical design of the power, ground, and clock networks is presented.

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“…Instructions are, then, free from false dependencies. This feature eliminates the need for register renaming unit, which consumes about 4% of the overall on-chip power in conventional RISC processors [20,21].…”

Section: Power Effective Embedded Pqp Corementioning

confidence: 99%

High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

2006

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Emerging high-level hardware description and synthesis technologies in conjunction with field programmable gate arrays (FPGAs) have significantly lowered the threshold for hardware development. Opportunities exist to integrate these technologies into a tool for exploring and evaluating microarchitectural designs especially for newly proposed architectures. This paper presents a prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using a hardware description language, we have created the Synthesizable model of a produced order parallel queue processor core for the integer subset parallel Queue architecture. A prototype implementation is produced by synthesizing the high-level model for the Stratix FPGA prototyping board. We show how to perform prototyping and optimizations to fully exploit the capabilities of the prototyped Queue processor core, while maintaining a common source base.

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A 300-MHz 64-b quad-issue CMOS RISC microprocessor

Cited by 53 publications

References 3 publications

High-performance microprocessor design

High-performance microprocessor design

Power considerations in the design of the Alpha 21264 microprocessor

High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

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