High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

Abdallah, Abderazek Ben; Yoshinaga, Tsutomu; Sowa, Masahiro

doi:10.1007/s11227-006-6719-5

Cited by 25 publications

(14 citation statements)

References 14 publications

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“…Their experiments show that the execution of programs on their queue machine has the potential of exploiting high levels of parallelism, while keeping code size smaller than an RISC instruction set. In our previous work [1][2][3], we proposed a novel 32-bit QueueCore processor with a 16-bit instruction set format. Our approach is to allow variables to be produced only once, but to be used many times.…”

Section: Introductionmentioning

confidence: 99%

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

et al. 2010

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This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computationbased processor. The instructions of a queue processor implicitly read and write their operands, making instructions short and the programs free of false dependencies. This characteristic allows the exploitation of maximum parallelism and improves code density. Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore. For a set of numerical benchmark programs, our compiler extracts more parallelism than the optimizing compiler for an RISC machine by a factor of 1.38. Through the use of QueueCore's reduced instruction set, we are able to generate 20% and 26% denser code than two embedded RISC processors.

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Section: Introductionmentioning

confidence: 99%

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

et al. 2010

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“…We proposed a novel high performance parallel queue processor architecture based on produced order queue instruction set architecture [2,3,10]. The key ideas of the queue computing model are the operands and results manipulation schemes.…”

Section: Introductionmentioning

confidence: 99%

“…In this state, it considers the shared storage unit as a circular queueregister [3]. The QSP32 switches between execution models by using a special hardware, named dynamic execution mode switch mechanism [6], where also sources and destination addresses for both modes are calculated dynamically.…”

Section: Introductionmentioning

confidence: 99%

Dual-execution mode processor architecture

2007

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In this research work, we propose a novel embedded dual-execution mode 32-bit processor architecture (QSP32), which supports queue and stack programming models. The QSP32 core is based on a high performance produced order parallel queue architecture and is targeted for applications constrained in terms of area, memory, and power requirements. The design focuses on the ability to execute queue programs and also to support stack programs without a considerable increase in hardware to the base queue architecture. A prototype implementation of the processor is produced by synthesizing the high level model for a target FPGA device. We present the architecture description and design results in a fair amount of details. From the design and evaluation results, the QSP32 core efficiently executes both queue and stack based programs and achieves on average about 65 MHz speed. In addition, when compared to the base single-mode architecture (PQP), the QSP32 core requires only about 2.41% additional hardware. Moreover, the prototype fits on a single FPGA device, thereby eliminating the need to perform multi-chip partitioning which results in a loss of resource efficiency.

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“…Algorithm 3. dup assignment (i) The length of the instruction set of the PQP is 2 byte [1]. The PQP has a special instruction, covop, which extends the value of the operand of the following instruction.…”

Section: Increase In Number Of Instructionsmentioning

confidence: 99%

“…In our previous work we have investigated and designed a Parallel Queue Processor (PQP) based on the Queue Computation Model [16,1,2]. The PQP breaks the rule of dequeueing to make a better utilization of the data in the operand queue.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model

Canedo

Abdallah

Sowa

Embedded and Ubiquitous Computing

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Abstract. Embedded systems very often demand small memory footprint code. A popular architectural modification to improve code density in RISC embedded processors is to use a dual instruction set. This approach reduces code size at the cost of performance degradation due to the greater number of reduced width instructions required to execute the same task. We propose a novel alternative for reducing code size by using a single reduced instruction set queue machine. We present a efficient code generation algorithm to insert additional instructions to be able to execute programs in the reduced instruction set. Our experiments show that the insertion of additional instructions is minimal and we demonstrate improved code size reduction of 16% over MIPS16, 26% over Thumb, and 50% over MIPS32 code. Furthermore, we show that our compiler without any optimization is able to extract about the same parallelism than fully optimized RISC code.

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High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

Cited by 25 publications

References 14 publications

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

Dual-execution mode processor architecture

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model

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