A 30/35GHz phased array transmitter front-end with &amp;#x003E;+14dBm Psat and 10&amp;#x00B0; phase/5-bit amplitude resolution for advanced beamforming

Pei, Yu; Chen, Y.; Leenaerts, D.M.W.; Slaats, Bianca; Zamanifekri, A.

doi:10.1109/esscirc.2014.6942049

Cited by 3 publications

(1 citation statement)

References 11 publications

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“…A phased array system contains many transmit/receive (T/R) front-end modules. The core functions of the T/R modules include signal amplification, phase shifting, and gain controlling [5,6,7,8,9,10]. Amplitude-controllable circuit plays a key role in phased-array systems.…”

Section: Introductionmentioning

confidence: 99%

A 25–35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS

Ding

Chen

et al. 2019

IEICE Electron. Express

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A mm-wave 5-bit digital attenuator with low RMS (root mean square) amplitude error and low phase variation is presented in 65 nm CMOS. The attenuator combines the PI/T-type topology with embedded switches and PI-type topology with the SPDT (single-pole-double-throw) switches to alleviate the insertion loss issue of the conventional PI/T-type topology with embedded switches in mm-wave frequency band, and achieves high attenuation range while maintaining compact chip size. The amplitude/phase calibration technique is proposed to reduce the RMS amplitude error/phase variation and improve the circuit robustness. The presented attenuator has been integrated in a Ka-band phased-array transmit front-end module and achieves 15.5 dB attenuation coverage with the step of 0.5 dB. The RMS amplitude error and RMS phase variation are 0.13-0.48 dB and 1.24-2.08°across 25-35 GHz, respectively. Especially, the proposed attenuator could achieve the RMS amplitude error of 0.13-0.25 dB if the operation frequency is limited to 26.9-31.4 GHz. The core chip size is 434 µm × 360 µm.

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