A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time

Abstract

3T1D is a non-destructive read DRAM cell with three transistors (T) and a gated diode (D). The gated diode acts as a storage device and an amplifier, leading to low voltage, high speed and high tolerance to variability, and comparing favorably to conventional 3T gain cell and 6T SRAM cell. Hardware measurements in 90 nm SOI showed the 3T1D achieved longer retention than the 3T. Retention, speed and scaling perspectives for future technology are presented.Introduction A 3T gain cell using the read device gate capacitor as storage is shown in Fig. 1a, also shown is a 3T1C cell with an additional storage capacitor (e.g. MOS, stack). In this paper, the 3T and the 3T1C are used interchangeably as a 3T cell. A novel dual port 3T1D DRAM cell is shown in Fig. 1b. The gated diode acts as a storage device and an amplifier for the cell voltage. Comparing to the 1T DRAM cell, the 3T1D has non-destructive read, as the cell charge is conserved during read. The gated diode voltage boosting [1, 2] leads to better retention and speed, higher tolerance to process variation than a 3T cell for the same voltage and cell size, or smaller area (~15%) for the same speed, retention and variability. Comparing to the 2T1D cell [1], for the same read device (rg) size, the 3T1D gate overdrive is higher as the source of rg is biased lower, hence faster with 10-20% more area. Without device mismatch issue found in 6T SRAM and the high tolerance to variability, the 3T1D as a potential alternative for high speed caches will be demonstrated in terms of retention and speed based on hardware and simulation. The low cell voltage of 3T1D combined with low leakage puts it ahead of the 3T and the 6T SRAM for addressing the voltage scaling and power issues. Hardware measurements of 3T1D and 3T arrays in 90 nm SOI, retention, speed, scaling for future technology will also be presented.The 3T1D memory cell The gate of the gated diode (gd) is the storage node, and is connected via a write device (wg) to a write bitline (BLw) forming the write path. A read device (rg) and a read select device (rs) are connected in series, between the read bitline (BLr) and GND, forming the read path. Separate write (WLw) and read (WLr) wordlines select the cells for write and read. Data is written and stored in gd as inversion charge for 1-data, and no charge for 0-data. BLw and BLr form a dual port cell, or can be tied together for a single port cell.By raising WLw high and holding WLr low, data is written into the storage node from BLw via wg, 0V for 0-data and high (VBLH) for 1-data. For read, WLr is pulsed from GND to high (VWLH). For read 1, the gd capacitance (Cgs) is large as the channel is on, the storage node voltage (Vc) is boosted high and turns rg on strongly. For read 0, Cgs is much smaller as the channel is off, and Vc is almost at GND and rg remains off. The difference in Vc between read 1 and 0 is more than that stored, achieving a voltage gain (typically 2 -4). Fig. 2 shows a 3T1D array cross-section. BLr is pre-charged to VBLHr. During read, BLr drops towa...

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

“…This is furthered by the decaying of the voltage at the storage node which makes subsequent read accesses slower. It was found that by strobing the read-wordline high continuously instead of sending read requests one after another, this problem can be alleviated as a result retention time reducing by nearly 20X to around hundreds of nanoseconds [8]. The decaying behavior of the storage node is replicated at the output of the sense amplifier.…”

“…3T1D CELL Alternatives to 6T based SRAM have been researched diligently for want of increased memory density and lower vulnerability to variations. One such proposal is the 3T1D cell proposed by Luk et al [8]. The capacitorless DRAM cell stores the data using a gated diode that is tied to the read-wordline as shown in Figure 1.…”

“…Unlike a 6T, the voltage level at the storage node is degraded and roughly about 0.6V dd . A strong T1 This can be avoided by increasing the threshold of the write driver [8]. The read operation is initiated by precharging (to V dd ) the readbitline and strobing the read-wordline.…”

“…The retention time of the cell can further be increased by holding the read-wordline at a negative voltage during idle state. This has shown to increase the retention rate by as much as 40X [8]. Liang et al have proposed a 3T1D-only cache architecture that offers 6T like performance but better robustness to process variations [10].…”

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

“…eDRAM features higher density and lower leakage in comparison to SRAM. Given the fact that the majority of commercial GPGPUs are operating at a relatively low frequency (600MHz-1GHz), modern eDRAM cells can easily meet the speed requirement [13,14] while providing doubled density and one order of magnitude lower leakage per bit [22,4]. Therefore, eDRAM potentially offers new opportunity in the design of on-chip memory structures on GPGPU.…”