A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

Weltin-Wu, Colin; Temporiti, Enrico; Baldi, Daniele; Cusmai, Marco; Svelto, F.

doi:10.1109/jssc.2010.2077370

Cited by 100 publications

(20 citation statements)

References 13 publications

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“…The adverse impact of nonlinearity on the generation of spurs in ADPLLs was originally discussed in [4]. The effects of nonlinearity are identical in both the digital-PLL topologies in Fig.…”

Section: B Spurs Due To Tdc Nonlinearitymentioning

confidence: 86%

“…In practice, if the delay elements of the TDC are shuffled, the effect of their mismatches is no longer periodic and the energy of fractional spurs is spread across the spectrum [5]. Same result is achieved by means of the sliding scale technique, which consists in adding a dithering sequence to the input of the TDC and subtracting it at its output [4]. A more effective solution consist in shaping in frequency the effect of mismatches, so that their energy is concentrated at high frequency and it is filtered out by the loop filter.…”

Section: B Spurs Due To Tdc Nonlinearitymentioning

confidence: 99%

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Nonlinearity cancellation in digital PLLs (Invited paper)

Levantino

Samori

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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One decade after their introduction into wireless applications, digital fractional-N phase-locked loops are becoming a competitive solution for products. Their ultimate level of spurs is often bounded by the resolution and the linearity of the time-to-digital converter. Although methods for mitigating its nonlinearity have been proven effective in lowering spurs, they typically increase the level of random noise. By contrast, digital-PLL architectures based on digital-to-time converters enable nonlinearity cancellation and spur reduction with no penalty on noise level, while reducing design complexity and power consumption

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Section: B Spurs Due To Tdc Nonlinearitymentioning

confidence: 86%

Section: B Spurs Due To Tdc Nonlinearitymentioning

confidence: 99%

Nonlinearity cancellation in digital PLLs (Invited paper)

Levantino

Samori

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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show abstract

“…While integrating a loop filter has been a challenging task in the conventional PLL design, removing the analog loop filter is considered an alternative solution in the recent PLL works [1][2][3][4][5][6][7][8][9][10][11][12][13]. However, the all-digital PLL (ADPLL) requires a high-resolution complex time-to-digital converter (TDC) which requires advanced CMOS technology.…”

Section: Design Issues In All-digital Pllmentioning

confidence: 99%

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Rhee

Wang

2011

Journal of Electrical and Computer Engineering

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This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

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“…DPLL can be insensitive to process, voltage, and temperature (PVT) variations in [5] and [6]. LC-tank DCOs achieve a higher operational frequency and lower phase noise as shown in [7] and [8].…”

Section: Introductionmentioning

confidence: 99%

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

Liu

Cheng

et al. 2016

IEICE Electron. Express

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This paper proposes an 8-phase all-digital phase-locked loop (ADPLL) for a low supply voltage application. The proposed multi-phase digitally controlled oscillator (MP-DCO) employs two sub-feedback loops at high operational frequencies. The proposed multi-phase-based time-to-digital converter (MP-TDC) uses the multi-phase scheme, which reduces its area, and uses a time amplifier to extend the timing resolution. With a low supply voltage, the DCO and the sense-amplifier based delay flip-flop (SA-DFF) use bulk-controlled techniques to improve the performance at high operational frequencies and setup/hold times, respectively. When the ADPLL output is 1.6 GHz at 0.6 V, the RMS and peak-to-peak jitters are 3.8 ps and 33.7 ps, respectively. The power consumption and core area are 9.1 mW at 1.6 GHz and 0.036 mm 2 in a 90 nm CMOS process, respectively. Thus, this clock generator is useful for low power systems.

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A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

Cited by 100 publications

References 13 publications

Nonlinearity cancellation in digital PLLs (Invited paper)

Nonlinearity cancellation in digital PLLs (Invited paper)

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

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