A 3.3 V-only 16 Mb flash memory with row-decoding scheme

Atsumi, S.; Umezawa, Akira; Kuriyama, M.; Banba, H.; Ohtsuka, N.; Tomita, N.; Iyama, Y.; Miyaba, T.; Sudoh, R.; Kamiya, Eiji; Tanimoto, M.; Hiura, Y.; Araki, Yoshiko; Sakagami, E.; Arai, Norihisa; Mori, Seiichi

doi:10.1109/isscc.1996.488506

Cited by 7 publications

(7 citation statements)

References 3 publications

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“…High voltage biases at the selected wordlines, bitlines, and source lines are necessary to selectively activate these phenomena on memory cells. An example of the bias conditions for a selected memory cell transistor is shown in Table II [1]. As already mentioned, in the case of the multitransistor process, should be set at a higher voltage than , while signals in the peripheral circuitry have level in all operation modes.…”

Section: Level Shifter Circuitmentioning

confidence: 99%

“…Recently, many Flash memories utilize a negative-gate erase scheme [1], [10]. In particular, this erase scheme is suitable for a single voltage supply Flash memory, because it realizes lower power consumption in erase mode than a source erase scheme.…”

Section: Level Shifter Circuitmentioning

confidence: 99%

“…5. For the negativeerase scheme, a double or triple well structure is introduced to realize a negative bias for wordlines in the erase mode [1], [3], and and are transistors fabricated in a p-well isolated from a p-type substrate by an n-well. The first level shifter converts a 0signal to a differential 0-output, while the second level shifter takes the 0signal and generates a -output.…”

Section: B High/low-level Shiftermentioning

confidence: 99%

“…For portable equipment applications, low power operation is important for long battery life. In order to decrease power consumption for a whole system, demand for a low supply voltage is increasing, and, in fact, of 3.3 V is the standard voltage for CPU's and RAM's in the market instead of of 5 V. Several 3.3-V operation Flash memories have been reported to meet this demand [1]- [5].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the transistor parameters, such as channel length, the oxide thickness, the threshold voltage, and the drain breakdown voltage, have to be tuned to sustain operation and the usual device scaling cannot be adopted for them. In order to solve this problem, a multitransistor process has been introduced for 3.3-V operation Flash memories [1], [2], [4], [5]. While a transistor is optimized with a device scaling for of 3 the program and the erase.…”

Section: Introductionmentioning

confidence: 99%

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Circuit techniques for 1.5-V power supply flash memory

Otsuka

Horowitz

1997

IEEE J. Solid-State Circuits

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We describe circuit techniques for a Flash memory which operates with a V DD of 1.5 V. For the interface between the peripheral circuits and the memory core circuits, two types of level shifter circuits are proposed which convert a V DD level signal into the high voltage signals needed for high performance. In order to improve the read performance at a low V DD , a new self-bias bitline voltage sensing scheme is described. This circuit greatly reduces the delay's dependence on bitline capacitance and achieves 19 ns reduction of the sense delay at low voltages. Multilevel storage sensing with this circuit is also discussed.

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Section: Level Shifter Circuitmentioning

confidence: 99%

Section: Level Shifter Circuitmentioning

confidence: 99%