A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS

Tai, Hung-Yen; Chen, Hung-Wei; Chen, Hsin-Shu

doi:10.1109/vlsic.2012.6243805

Cited by 16 publications

(10 citation statements)

References 3 publications

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“…In the balanced state, and . Hence (17) Therefore, the comparator random offset caused by mismatch between M1 and M2 can be derived as (18) Assume mismatch between M3 and M4 is similar to that between M1 and M2, the current difference flowing across M3 and M4 can be expressed as (19) By using the first order approximation of Taylor expansion, (19) can be rewritten as (20) Combining with the transconductance of input-transistors M1 and M2 (21) Then, the input-referred comparator offset due to the mismatch between M3 and M4 can be derived as (22) where . Consequently, random offset caused by the mismatch between M3 and M4 is (23) Similarly, random offset caused by the mismatch between M5 and M6 is (24) where .…”

Section: A Dynamic Latched Comparator Designmentioning

confidence: 99%

“…At 20 kS/s, the ADC consumes 38 nW from a 0.6-V supply. The performance of the ADC is summarized in Table III, where comparison with other state-of-the-art SAR ADCs [22]- [26] is listed. It can be seen that the proposed SAR ADC achieves excellent performance despite it is implemented in 0.18-CMOS and adopts the 18-fF unit capacitor.…”

Section: Sar Control Logic Designmentioning

confidence: 99%

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A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-<formula formulatype="inline"><tex Notation="TeX">$\mu{\rm m}$</tex> </formula> CMOS for Medical Implant Devices

Zhu

Liang

2015

IEEE Trans. Circuits Syst. I

114

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This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis of comparator offset voltages is made. Based on the analysis, the comparator is optimized by only adjusting transistor sizes without any particular offset cancellation. As a result, when the common-mode input voltage varies from 300 mV to 450 mV at a 0.6 V supply, the offset voltage is optimized to be about 6 mV with a fluctuation of only 0.15 mV, as revealed by Monte Carlo simulations. A prototype of the proposed ADC was fabricated in 0.18 1P6M CMOS technology, which occupies an active area of only . At a 0.6-V supply and 20 kS/s sampling rate, the ADC achieves an SNDR of 58.3 dB and a power consumption of 38 nW, resulting in a figure of merit (FOM) of 2.8 fJ/conversion-step.

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Section: A Dynamic Latched Comparator Designmentioning

confidence: 99%

Section: Sar Control Logic Designmentioning

confidence: 99%

A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-<formula formulatype="inline"><tex Notation="TeX">$\mu{\rm m}$</tex> </formula> CMOS for Medical Implant Devices

Zhu

Liang

2015

IEEE Trans. Circuits Syst. I

114

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show abstract

“…Another technique is known as a generalized non-binary algorithm, where a non-integer ratio of capacitances is not needed [33], [43], [45][46][47], [52], [54], [58], [59], [61], [63], [65], [69]. For example, a non-binary weight such as {128, 46,26,20,14,8,6,4,2,1} instead of the binary weight of {128, 64,32,16,8,4,2,1} was used to obtain 8-bit resolution [69].…”

Section: B Circuit Implementationmentioning

confidence: 99%

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

Waho

2014

2014 IEEE 44th International Symposium on Multiple-Valued Logic

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Low-power successive-approximation (SA) analogto-digital converters (ADCs) are attracting increasing attention these days in biomedical and sensor network applications. The binary search algorithm is one of the basic idea behind how they obtain a binary code representing an analog input. In practice, the imperfectness of analog circuit elements sometimes results in decision errors and decreases the resolution of A/D conversion. Thus, making accurate decisions using imperfect elements is a big challenge. This paper surveys one solution known as non-binary SA with redundancy as well as related topics and its application to state-of-the-art SA ADCs.

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“…Most ADCs are required to operate at ultra-low voltage and a low sampling rate of 1 kS/s-1 MS/s in such devices. Simple structure, medium resolution and low energy consumption are the characteristics of SAR ADC, which makes it a popular candidate in various biomedical applications [1][2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

A 2.67 fJ/c.‐s. 27.8 kS/s 0.35 V 10‐bit successive approximation register analogue‐to‐digital converter in 65 nm complementary metal oxide semiconductor

Zhu

Qiu

Shen

et al. 2014

IET Circuits, Devices & Systems

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A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor Abstract: A design of a 10-bit 27.8 kS/s 0.35 V ultra-low power successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. Nano-watt range power consumption is achieved thanks to the proposed segmented-capacitor array structure and ultra-low voltage design. To facilitate ultra-low voltage operation, a bulk-driven based fully dynamic comparator is proposed. A novel latched dynamic logic cell is introduced to eliminate decision error caused by leakage current. Boosting technique is introduced in digital-to-analogue converter (DAC) driving switch to relieve non-linearity. A new double-boosted sample switch is employed to reduce leakage current and improve sampling linearity. The ADC was fabricated in 65 nm complementary metal oxide semiconductor. Drawing 25.2 nW from a single 350 mV supply, the ADC achieves 52.14 dB signal-to-noise distortion ratio and 8.4-bit effective number of bits resulting in a figure-of-merit of 2.67 fJ/ conversion-step.

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A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS

Cited by 16 publications

References 3 publications

A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-<formula formulatype="inline"><tex Notation="TeX">$\mu{\rm m}$</tex> </formula> CMOS for Medical Implant Devices

A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-<formula formulatype="inline"><tex Notation="TeX">$\mu{\rm m}$</tex> </formula> CMOS for Medical Implant Devices

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

A 2.67 fJ/c.‐s. 27.8 kS/s 0.35 V 10‐bit successive approximation register analogue‐to‐digital converter in 65 nm complementary metal oxide semiconductor

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