A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-<formula formulatype="inline"><tex Notation="TeX">$\mu{\rm m}$</tex> </formula> CMOS for Medical Implant Devices

Abstract

This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis of comparator offset voltages is made. Based on the analysis, the comparator is optimized by only adjusting transistor sizes without any particular offset cancellation. As a result, when the common-mode input voltage varies from 300 mV to 450 mV at a 0.6 V supply, the offset voltage is optimized to be about 6 mV with a fluctuation of only 0.15 mV, as revealed by Monte Carlo simulations. A prototype of the proposed ADC was fabricated in 0.18 1P6M CMOS technology, which occupies an active area of only . At a 0.6-V supply and 20 kS/s sampling rate, the ADC achieves an SNDR of 58.3 dB and a power consumption of 38 nW, resulting in a figure of merit (FOM) of 2.8 fJ/conversion-step.

A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

“…By connecting one-side plates of all capacitors to an identical voltage, it can be guaranteed that DACs consume zero energy in this phase. 24 So, B1 is resolved without any switching energy, and voltage shift of (V ref =4) occurs in one of the DACs. As a case study assuming B1 = 1, voltage shift of capacitor arrays can be described based on charge conversion expression (Q old ¼ Q new ) as below:…”

“…Regarding detected B1, the bottom plates of DAC1 or DAC2 are connected to . By connecting one‐side plates of all capacitors to an identical voltage, it can be guaranteed that DACs consume zero energy in this phase 24 . So, B1 is resolved without any switching energy, and voltage shift of ( ) occurs in one of the DACs.…”

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

“…This overhead includes the generation and distribution of multiple clock phases, the distribution of the input and reference signals to all of the Due to the high compatibility of SAR ADCs with digital CMOS and modern deep submicron technologies, they have become very popular in recent years. Depending on the topology and fabrication technology, SAR ADCs can achieve a wide range of characteristics as standalone ADCs, such as ultralow power [55,56], high speed [57], and high resolution [58]. Furthermore, they can be used as a part of a hybrid ADC, such as in [4,8,59].…”

Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices

“…Often, the transducers are commanded by a complementary metal-oxide semiconductor (CMOS) circuitry. The advantages of the combination of implantable sensors, CMOS electronics and integration technologies have been revealed by many authors [15][16][17][18][19][20][21][22]. In 2019, Angotzi et al presented an implantable CMOS biosensor for simultaneous large-scale neural recording.…”