A 2.67 fJ/c.‐s. 27.8 kS/s 0.35 V 10‐bit successive approximation register analogue‐to‐digital converter in 65 nm complementary metal oxide semiconductor

Abstract

A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor Abstract: A design of a 10-bit 27.8 kS/s 0.35 V ultra-low power successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. Nano-watt range power consumption is achieved thanks to the proposed segmented-capacitor array structure and ultra-low voltage design. To facilitate ultra-low voltage operation, a bulk-driven based fully dynamic comparator is proposed. A novel latched dynamic logic cell is introduced to eliminate decision error caused by leakage current. Boosting technique is introduced in digital-to-analogue converter (DAC) driving switch to relieve non-linearity. A new double-boosted sample switch is employed to reduce leakage current and improve sampling linearity. The ADC was fabricated in 65 nm complementary metal oxide semiconductor. Drawing 25.2 nW from a single 350 mV supply, the ADC achieves 52.14 dB signal-to-noise distortion ratio and 8.4-bit effective number of bits resulting in a figure-of-merit of 2.67 fJ/ conversion-step.

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“…This Work Centurelli et al 3 Saranovac 22 Lin and Hsieh 23 Xiaofeng et al 24 Zhu et al 25 Keskin 26 Sarafi et al 27 Fayomi et al 28 Zhou …”

Design optimisation procedure for digital mismatch compensation in latch comparators

“…This model can be generalised to dynamic latch circuits including latch comparators. Thus, one general technique of the offset calibration is to introduce a controlled capacitor imbalance ΔC opposite to the circuit devices mismatch allowing to compensate any inherent offset error V OS in accordance with (2). The capacitive trimming ΔC can be either a capacitive charge injection imbalance or a capacitive value imbalance.…”

“…The latter increments and generates a new N-bit control word p, which reduces the trimming capacitor. This creates a negative capacitor imbalance −|ΔC| = C 1 −C 2 , which creates a negative offset voltage in accordance with (2). The trimming voltage is then added to the positive input offset and compensates the inherent devices mismatch.…”

“…Latch comparators, also known as regenerative comparators, are finding wide spread use in many high-performance systems such as analogue-to-digital converters (ADCs) [1][2][3] and static random access memory bit line detectors [4][5][6], as well as radio-frequency transceivers and low-power applications [7]. These dynamic circuits include positive feedback loops and provide high-speed operation, reduced silicon area and low-power consumption.…”

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“…In recent years, ADCs have been continuously pushed towards their performance limits, which have seen a drastic decrement in their power consumption. Many highspeed ADCs like flash ADC require low power and high-speed comparators [1][2][3][4][5][6]. In a given technology, the speed of operation is proportional to the size of the differential input, which results in higher performance at the cost of power and the die area.…”