A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Kull, Lukas; Toifl, Thomas; Schmatz, M.; Francese, Pier Andrea; Menolfi, Christian; Braendli, Matthias; Kossel, Marcel; Morf, Thomas; Andersen, Tom Løgstrup; Leblebici, Yusuf

doi:10.1109/jssc.2013.2279571

Cited by 256 publications

(73 citation statements)

References 12 publications

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“…A recent research study demonstrates the availability of ADCs in 32 nm CMOS that consume only 3.1 mW at 8-bit and 1.2 GSamples/s [13]. This not only supports Nyquist sampling for SKA1-Low, but also for SKA instruments with wider and higher frequency band requirements.…”

Section: Power Parameters and Scaling Rules -Station And Cspmentioning

confidence: 66%

Holistic power analysis of implementation alternatives for a very large scale synthesis array with phased array stations

Anghel

Jongerius

Dittmann

et al. 2014

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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The Square Kilometre Array (SKA) will be the largest radio telescope in the world, generating data at Pb/s rates. Real-time processing will require 10 18 compute operations per second and system operating costs will be dominated by energy consumption. In this paper we explore design options for the aperture array of the first SKA construction phase and provide lower bounds on their power consumption. We analyze the system's components from the antenna front-end to the central signal processor and identify the main power consumers. We compare ASIC-based and FPGA-based data processing pipelines and show that ASICs can lead to 1.6 to 4 times more power efficiency.

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Section: Power Parameters and Scaling Rules -Station And Cspmentioning

confidence: 66%

Holistic power analysis of implementation alternatives for a very large scale synthesis array with phased array stations

Anghel

Jongerius

Dittmann

et al. 2014

2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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“…Values for the constants 0 and measured by Kull et al, (2013) for a modern nanometre CMOS technology are also used in this analysis. In order to further simplify the expression (A5) and remove the unknown varying quantity , the result of Waters et al (2015) is used.…”

Section: Discussionmentioning

confidence: 99%

Analysis of feedback predictive encoder based ADCs

Scanlan

O’Hare

Halton

et al. 2017

COMPEL

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ABSTRACT:Purpose-The purpose of this paper is to present analysis of the feedback predictive encoder based ADC (Analog-to-Digital Converter).Design/methodology/approach-The use of feedback predictive encoder based ADCs presents an alternative to the traditional two stage pipeline ADC by replacing the input estimate producing first stage of the pipeline, with a predictive loop that also produces an estimate of the input signal. Findings-The overload condition for feedback predictive encoder ADCs is dependent oninput signal amplitude and frequency, system gain and filter order. The limitation on the practical useable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum useable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimisation of the power consumption.Originality/value-This paper presents a methodology to optimise the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimisation of power consumption based on the allocation of time between the gain stage and the SAR ADC operation is investigated.The lower bound of power consumption for this architecture is estimated. Paper Type-Research Paper

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“…In fact, if a comparison cycle takes a very long time, the offset calibration cycle will be skipped but it will not degrade the offset calibration. A similar scheme has been recently used in [17].…”

Section: Calibration Of the Comparator Offsetmentioning

confidence: 99%

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Reyes

Paulina²,

Sánchez³

et al. 2015

Analog Integr Circ Sig Process

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A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to AE25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.

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A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Cited by 256 publications

References 12 publications

Holistic power analysis of implementation alternatives for a very large scale synthesis array with phased array stations

Holistic power analysis of implementation alternatives for a very large scale synthesis array with phased array stations

Analysis of feedback predictive encoder based ADCs

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

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