A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology

Bulzacchelli,; Beukema,; Storaska,; Hsieh,; Rylov,; Furrer,; Gardellini,; Prati,; Menolfi,; Hanson,; Hertle,; Morf,; Sharma, Vivek; Kelkar,; Ainspan,; Kelly,; Ritter,; Garlett,; Callan,; Toifl,; Friedman,

doi:10.1109/isscc.2012.6177031

Cited by 22 publications

(10 citation statements)

References 4 publications

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“…5) is cancelled. Signals developed across the integration and replica load capacitors C INT are level-shifted via switched series capacitors C S [5] to ensure proper common-mode levels at the comparator input. The use of a differential comparator and replica integrator also reduces the sensitivity of the circuit to power supply noise.…”

Section: Phase Rotatormentioning

confidence: 99%

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Dickson

Liu

Agrawal

et al. 2015

2015 IEEE Custom Integrated Circuits Conference (CICC)

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A 16x16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The I/O also includes an 8:1 TX serializer with 8-phase clocking, and an active-inductor-based RX CTLE whose outputs form current mirrors with the inputs of the RX samplers. A phase rotator based on currentintegrating phase interpolator cores is described, with architecture and circuit improvements to performance as compared to prior art. 16-Gb/s link measurements over Megtron-6 traces demonstrate efficiencies of 1.8pJ/bit (0.75" traces) and 1.9pJ/bit (10" traces) with >30% timing margin, with the TX, RX, and PLL operating from 1V supplies.

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Section: Phase Rotatormentioning

confidence: 99%

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Dickson

Liu

Agrawal

et al. 2015

2015 IEEE Custom Integrated Circuits Conference (CICC)

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“…They are required to cover a wide range of frequencies and maintain high performance while being power and area efficient [1]. This poses stringent requirements on the clock generation and distribution circuits to maximize the overall I/O performance.…”

Section: Introductionmentioning

confidence: 99%

“…This poses stringent requirements on the clock generation and distribution circuits to maximize the overall I/O performance. To push data rates to 25Gb/s and beyond, half-rate links with oversampled CDRs and quarter-rate architectures have been used [1][2], both of which require generating quadrature phases with low power and area. In [1], an LC-VCO followed by dividers generates half-rate clocks for both TX and RX in a 28Gb/s transceiver.…”

Section: Introductionmentioning

confidence: 99%

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS

Elshazly

Balankutty

Huang

et al. 2014

2014 Symposium on VLSI Circuits Digest of Technical Papers

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A highly digital quadrature clock generator using a digital DLL that employs a digital loop filter and digitally-calibrated replica-based regulator is presented. The proposed DLL combines the advantages of both analog and digital loop-filters of conventional architectures to implement a wide-range, energy efficient, highly digital, and high performance quadrature clock generator. To suppress supply-noise, we propose an LDO that combines fast/slow paths with a replica-load to achieve better than 20dB rejection with small area and low power. Fabricated in Intel's 14nm CMOS process, the proposed digital DLL operates over a wide range of output frequencies (2GHz-to-7.5GHz). At 7GHz, it achieves 176fs rms /2.7ps pp long-term jitter while consuming 4.4mW. The DLL is 4X smaller than state-of-the art designs and occupies an active area of 0.0024mm 2 .

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“…A lowpower low-cost serial link is needed for the next-generation peripheral interface that can scale to 32Gb/s per lane. Recent publications have demonstrated 28 to 32Gb/s rates [1][2]. However, the circuit power and channel characteristics are not suitable for mainstream PC and mobile markets.…”

mentioning

confidence: 99%

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

Jaussi

Balamurugan

Hyvonen

et al. 2014

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

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Peripheral I/O data-rates for PCs and mobile computing platforms continue to scale to meet high-bandwidth applications including high-resolution displays and large-capacity external storage. The bandwidth requirements will soon exceed the data-rates of current standards such as PCI Express and USB. A lowpower low-cost serial link is needed for the next-generation peripheral interface that can scale to 32Gb/s per lane. Recent publications have demonstrated 28 to 32Gb/s rates [1][2]. However, the circuit power and channel characteristics are not suitable for mainstream PC and mobile markets. A low-profile connector and cable assembly prototype is developed for these markets, where the link architecture and design are optimized for the channel characteristics. This paper describes a data-rate-scalable 32Gb/s serial link that features a bidirectional transceiver, source-series terminated (SST) 3-tap FFE, a continuous-time linear equalizer (CTLE) with an active inductor, a 6-tap DFE, and clock calibration and adaptation circuitry. Figure 26.2.1(a) illustrates the interconnect topology. The primary components are PCBs, packages, connectors and cable. The 8-lane cable assembly consists of consumer-grade 32AWG shielded twisted pair copper wires. The height and width of the connector are 3mm and 13mm, respectively. The bidirectional transceiver architecture is shown in Fig. 26.2.1(b). An LC-VCO-based PLL generates a quarter-rate clock that is distributed to each transceiver lane using regulated CMOS buffers similar to [3]. In order to save power, the transceivers are grouped into 4 lanes to form a bundle. The DLL and clock multiplier are common to the 4 lanes and are included in the bundle clock circuitry. The TX is based on a half-rate clock architecture, while the RX uses a quarter-rate clock architecture. After the DLL, the quarter-rate clock is multiplied to half-rate and distributed locally to 4 TXs. The output stage is a low-swing segmented SST driver using NMOS devices for channel termination. 3-tap TX pre-emphasis is implemented using switching devices to short differential outputs similar to [4]. The RX front-end consists of a CTLE and 6-tap DFE. The CTLE has an active inductor to provide up to 4dB of peaking while minimizing silicon area [5]. Other than the LC-VCO, no passive inductors are used for bandwidth extension or I/Opad-capacitance reduction. A quadrature clock generator (Q-Gen) provides I/Q clocks for the 4-way interleaved DFE. Across <12dB loss channels and up to 12Gb/s, a separate 2-way interleaved low-power (LP) latch with 2× oversampled CDR is used to reduce power consumption by disabling the CTLE and DFE. There are two separate CDR logic blocks, one in the lane and one in the bundle, that independently control the quadrature phase interpolator (PI). The bundle CDR aggregates the phase-recovery information from all 4 lanes.To minimize the area and pad capacitance of the bidirectional transceiver, the SST TX can be configured to be RX termination as shown in Fig. 26.2.2. When functioning as an output...

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A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology

Cited by 22 publications

References 4 publications

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

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A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology

Cited by 22 publications

References 4 publications

A 1.8-pJ/bit 16&#x00D7;16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

A 1.8-pJ/bit 16&#x00D7;16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

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A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration