26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

Abstract

Peripheral I/O data-rates for PCs and mobile computing platforms continue to scale to meet high-bandwidth applications including high-resolution displays and large-capacity external storage. The bandwidth requirements will soon exceed the data-rates of current standards such as PCI Express and USB. A lowpower low-cost serial link is needed for the next-generation peripheral interface that can scale to 32Gb/s per lane. Recent publications have demonstrated 28 to 32Gb/s rates [1][2]. However, the circuit power and channel characteristics are not suitable for mainstream PC and mobile markets. A low-profile connector and cable assembly prototype is developed for these markets, where the link architecture and design are optimized for the channel characteristics. This paper describes a data-rate-scalable 32Gb/s serial link that features a bidirectional transceiver, source-series terminated (SST) 3-tap FFE, a continuous-time linear equalizer (CTLE) with an active inductor, a 6-tap DFE, and clock calibration and adaptation circuitry. Figure 26.2.1(a) illustrates the interconnect topology. The primary components are PCBs, packages, connectors and cable. The 8-lane cable assembly consists of consumer-grade 32AWG shielded twisted pair copper wires. The height and width of the connector are 3mm and 13mm, respectively. The bidirectional transceiver architecture is shown in Fig. 26.2.1(b). An LC-VCO-based PLL generates a quarter-rate clock that is distributed to each transceiver lane using regulated CMOS buffers similar to [3]. In order to save power, the transceivers are grouped into 4 lanes to form a bundle. The DLL and clock multiplier are common to the 4 lanes and are included in the bundle clock circuitry. The TX is based on a half-rate clock architecture, while the RX uses a quarter-rate clock architecture. After the DLL, the quarter-rate clock is multiplied to half-rate and distributed locally to 4 TXs. The output stage is a low-swing segmented SST driver using NMOS devices for channel termination. 3-tap TX pre-emphasis is implemented using switching devices to short differential outputs similar to [4]. The RX front-end consists of a CTLE and 6-tap DFE. The CTLE has an active inductor to provide up to 4dB of peaking while minimizing silicon area [5]. Other than the LC-VCO, no passive inductors are used for bandwidth extension or I/Opad-capacitance reduction. A quadrature clock generator (Q-Gen) provides I/Q clocks for the 4-way interleaved DFE. Across <12dB loss channels and up to 12Gb/s, a separate 2-way interleaved low-power (LP) latch with 2× oversampled CDR is used to reduce power consumption by disabling the CTLE and DFE. There are two separate CDR logic blocks, one in the lane and one in the bundle, that independently control the quadrature phase interpolator (PI). The bundle CDR aggregates the phase-recovery information from all 4 lanes.To minimize the area and pad capacitance of the bidirectional transceiver, the SST TX can be configured to be RX termination as shown in Fig. 26.2.2. When functioning as an output...

Performance of edge tap decision feedback equalization methods for wireline receivers

“…As more ISI is added at later post-cursor locations, the number of crossings for the unequalized edge increases and T JPP becomes larger. These extra edge crossings can shift the lock point of the clock-anddata recovery (CDR) and reduce the data eye opening, and this may reduce the CDR jitter tolerance [8,12,13].…”

“…For example, both edge samples may be equalized with +h 1 , or both with -h 1 , or one even/odd edge path may use +h 1 and the other path may use -h 1 . The average probability for each polarity of edge sample is 50%, and if a static polarity of tap 1 is applied to an edge sample path, it will be correct 25% of the time on average [8]. To benefit from tap 1 equalization using Method 2B, the CDR should only update the lock position based on edge samples that receive the correct polarity of tap 1 feedback.…”

“…Recent advances in design techniques have led to direct-feedback DFEs operating at 66-Gbps [1]. Additionally, loop-unrolled DFEs are often used to avoid the settling time of the latch and summer, and to provide additional design flexibility [2][3][4][5][6][7][8][9].…”

“…2. This example depicts a half-rate clock or double data rate (DDR) DFE, a commonly used architecture for its reduced clock rate compared to full-rate DFEs [2][3][4][5][6][7][8][9][10]. It is also possible for the output of one MUX to drive the select control of the other MUX directly if full flip-flops are used before the MUX, subject to the considerations in [2,4].…”

A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

“…2, which includes 8 bidirectional transceiver lanes [5]. The bidirectional lanes support asymmetric BW operation through the use of unequal transmit and receive rates or by configuring the lanes to 0018-9200 © 2014 IEEE.…”