A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Jain, Shailendra; Khare, Surhud; Yada, Satish; Ambili, V; Salihundam, Praveen; Ramani, Shiva; Muthukumar, Sriram; Srinivasan, Mahesh; Kumar, Anand; Gb, Shasi Kumar; Ramanarayanan, R.; Erraguntla, Vasantha; Howard, Jason D.; Vangal, Sriram; Dighe, Saurabh; Ruhl, G.; Aseron, Paolo; Wilson, H.; Borkar, Nitin; De, Vivek; Borkar, S.

doi:10.1109/isscc.2012.6176932

Cited by 162 publications

(73 citation statements)

References 3 publications

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“…We have chosen a very simple processor architecture with one core and in-order execution, resembling a recently fabricated Intel processor for hybrid Vcc operation although not suited for the ultra-low-cost market [10]. Both on-chip L1 data (DL1) and instruction (IL1) caches implement the proposed design.…”

Section: A Methodologymentioning

confidence: 99%

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Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Marić¹,

Abella²,

Valero³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 C) required for new market segments such as body, urban life and environment monitoring. Caches have been shown to be the highest energy and area consumer in those chips.This paper proposes a novel, hybrid-operation (high Vcc, ultralow Vcc), single-Vcc domain cache architecture based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with Error Detection and Correction (EDC) features for high reliability and performance predictability. Our architecture is proven to largely outperform existing solutions in terms of energy and area.

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Section: A Methodologymentioning

confidence: 99%

“…We have set Vcc to 1V and 350mV for HP and ULE mode respectively. Operating frequencies are set to 1GHz for HP mode, and 5MHz for ULE mode, which is in line with the Intel processor for hybrid Vcc operations [10].…”

Section: A Methodologymentioning

confidence: 99%

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Marić¹,

Abella²,

Valero³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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show abstract

“…Recently, on-chip timing monitors and adaptive voltage scaling (AVS) circuits [1,2,3,4,5,6,7,8,9, 10] had been proposed to reduce the design-time margin caused by severe PVT (Process, Voltage, and Temperature) variations, such as error detection and correction techniques of Razor [1,10], ARM error detection [2], Razor-lite [3], Bubble Razor [4] and improved monitor [8], as well as errorprediction techniques of Canary Flip-flop [5], HEPP [6] and replica circuits in reconfigurable devices [9]. They use timing monitors to detect or predict timing errors, and then adaptively tune the supply voltage accordingly to reduce power.…”

Section: Introductionmentioning

confidence: 99%

Timing monitoring paths selection for wide voltage IC

Shan

Dai

Shi

et al. 2016

IEICE Electron. Express

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Wide voltage range circuit has got widespread attention where in-situ timing monitoring based adaptive voltage scaling (AVS) becomes necessary to reduce the design margin. However, the severe PVT variations across near-threshold to super-threshold cause too many critical paths to be monitored. Here activation oriented monitoring paths selection method is proposed to reduce the monitored paths for wide voltage IC. The minimum delay value of the longest activated path is found by dynamic timing analysis and set as the selection threshold. Those paths longer than this threshold by STA analysis are selected to be monitored. Applied on a 40 nm AVS Systemon-Chip, it reduces the monitoring paths to only 22% of all critical paths with remarkable power gains under 0.6 V-1.1 V.

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“…The sub-threshold operation of application-specific logic or an Intel architecture, 32-bit (IA-32) core, operating at near-threshold voltage, shows the prospective power benefits of low-voltage operation [2,3]. Low voltage operation of the processor core incurs two limiting factors.…”

Section: Introductionmentioning

confidence: 99%

“…The performance monitoring circuit prevents operational failure of the processor core. Jain et al [3] employed variation-aware pruning of standard cells for reliable lowvoltage operation. Das et al [4] proposed the shadow latch with meta-detector to identify circuit failures.…”

Section: Introductionmentioning

confidence: 99%

80μW/MHz 0.68V Ultra Low-Power Variation-Tolerant Superscalar Dual-Core Application Processor

Kwon

Lee²,

Shin³

et al. 2015

IEIE Transactions on Smart Processing and Computing

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Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of 80 W/MHz. The operating frequency of the core reaches 850MHz at 1.2V.

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A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Cited by 162 publications

References 3 publications

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Timing monitoring paths selection for wide voltage IC

80μW/MHz 0.68V Ultra Low-Power Variation-Tolerant Superscalar Dual-Core Application Processor

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