A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-V&lt;inf&gt;TH&lt;/inf&gt; read-port, and offset cell VDD biasing techniques

Chen, Ming-Pin; Chen, Lai-Fu; Chang, Meng-Fan; Yang, Shu-Meng; Kuo, Yao-Jen; Wu, Jen-Ming; Ho, Mon−Shu; Su, Hsiu-Yun; Chu, Yuan-Hua; Wu, Wen-Ching; Yang, Tzong–Jer; Yamauchi, Hiroyuki

doi:10.1109/vlsic.2012.6243815

Cited by 3 publications

(3 citation statements)

References 2 publications

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“…A 7T bitcell with less than 15% area penalty compared to the 6T bitcell was demonstrated in Ref. [27]. However, this topology incurs short-circuit current from unselected bitcells that store V DD on their read device during read operations in this 7T-like topology.…”

Section: Memory Design Considerations In Ulp Sensor Nodesmentioning

confidence: 99%

Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes

Lee

Yoon

Kim

et al. 2013

IPSJ Transactions on System LSI Design Methodology

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Designing an ultra-low power sensor node requires careful consideration of the system-level energy budget. Depending on applications, various components can dominate total energy. In this paper, we review three different system energy budget scenarios where any of the microprocessor, memory, and timer of a sensor node can dominate the energy budget. The design space and corresponding trade-offs for these three components are explored to suggest guidelines for the design of ultra-low power sensor nodes.

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Section: Memory Design Considerations In Ulp Sensor Nodesmentioning

confidence: 99%

Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes

Lee

Yoon

Kim

et al. 2013

IPSJ Transactions on System LSI Design Methodology

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“…Larger cell topologies, such as 8T register file cells [14], and 10T cells with column interleaving support [15], provide improved cell stability at the expense of area and power by decoupling read and write operations. Literature also includes more exotic examples of asymmetrical cells, such as 5T [16], and 7T [17], cells. Another significant design centric solution involved the change from a ''tall'' to a ''wide'' cell design [18].…”

Section: Low Power Memory Design Trendsmentioning

confidence: 99%

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip

Eltawil

Engel

Geuskens

et al. 2013

Microprocessors and Microsystems

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a b s t r a c tAs systems-on-chip increase in complexity, the underlying technology presents us with significant challenges due to increased power consumption as well as decreased reliability. Today, designers must consider building systems that achieve the requisite functionality and performance using components that may be unreliable. In order to do so, it is crucial to understand the close interplay between the different layers of a system: technology, platform, and application. This will enable the most general tradeoff exploration, reaping the most benefits in power, performance and reliability. This paper surveys various cross layer techniques and approaches for power, performance, and reliability tradeoffs are technology, circuit, architecture and application layers.

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“…It is particularly eligible for power-efficient applications where the power consumption is highly constrained while the performance requirement is secondary. Accordingly, many power-hungry digital systems [5][6][7][8][9] and low-power memories [10][11][12][13][14] benefit tremendously from sub-threshold circuits.…”

Section: Introductionmentioning

confidence: 99%

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

Wen¹,

Liu²,

Zhang³

et al. 2020

IET Circuits, Devices & Systems

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In this study, the authors propose a sub-threshold standard cell library in which the quintessence is a quasi-Schmitttrigger logic design scheme and the inverse narrow width effect aware sizing method. The techniques can improve the I onto -I off ratio of the logic cells effectively and provide a significant suppression in leakage current, enhancing the robustness of the circuits. Simulation results show that the NAND3 and NOR3 logics with the new techniques achieve 40-60% and 30-50% reductions in leakage power compared with conventional logic circuits, respectively, when the voltage is scaled down to subthreshold region. Again, they also exhibit considerable improvements in process variation immunity and power-delay product.

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A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-V<inf>TH</inf> read-port, and offset cell VDD biasing techniques

Cited by 3 publications

References 2 publications

Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes

Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

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