2013
DOI: 10.2197/ipsjtsldm.6.17
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Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes

Abstract: Designing an ultra-low power sensor node requires careful consideration of the system-level energy budget. Depending on applications, various components can dominate total energy. In this paper, we review three different system energy budget scenarios where any of the microprocessor, memory, and timer of a sensor node can dominate the energy budget. The design space and corresponding trade-offs for these three components are explored to suggest guidelines for the design of ultra-low power sensor nodes.

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Cited by 8 publications
(2 citation statements)
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“…Sensors are usually positioned randomly in a large zone; if one of the sensors depletes its energy, replacing the power supply becomes difficult, especially in hostile inaccessible environments, and energy holes emerge [10]. Furthermore, the power of a sensor node decreases during the transmission of data [11,12].…”
Section: Introductionmentioning
confidence: 99%
“…Sensors are usually positioned randomly in a large zone; if one of the sensors depletes its energy, replacing the power supply becomes difficult, especially in hostile inaccessible environments, and energy holes emerge [10]. Furthermore, the power of a sensor node decreases during the transmission of data [11,12].…”
Section: Introductionmentioning
confidence: 99%
“…Fig.2shows the direction of cell leakage and bit line leakage[20].The 1T1C DRAM dissipates leakage current (mostly I sub ) form access transistor and dielectric current (I d ) from the storage capacitor. This is shown in Fig.3[21].Sub-threshold leakage current is the primary source of power dissipation in the idle SRAM and DRAM cells, it is characterized by the following expressions[22]:…”
mentioning
confidence: 99%