A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

Calhoun, Benton H.; Chandrakasan, Anantha P.

doi:10.1109/jssc.2006.891726

Cited by 366 publications

(203 citation statements)

References 19 publications

Supporting

Mentioning

200

Contrasting

Unclassified

Order By: Relevance

“…To reduce the read access time, M7 can be implemented using an LVT transistor, however this increases the off-leakage of the buffer, reducing the number of bitcells in a column. This leakage can be reduced through several techniques, such as implementing M8 with an HVT implant, or adding an additional stacking transistor, as shown by Calhoun et al [2] in their 10T sub-threshold cell.…”

Section: Read Operationmentioning

confidence: 99%

“…Subthreshold leakage is a problem for all system components, but it is a particularly important problem in on-chip caches, as they are a growing fraction of the total number of microprocessor devices. Today, SRAMs comprise a significant percentage of the total area and total power for many digital chips, and this is only expected to rise [2]. Furthermore, leakage power is becoming the primary factor of cache power consumption due to the large number of storage cells (cross-coupled inverters) in on-chip caches, where there is no stacking effect to reduce the leakage current.…”

Section: Introductionmentioning

confidence: 99%

“…Over the years, many techniques have been proposed for the reduction of SRAM power consumption [2][3][4][5][6][7], but the most efficient way to reduce the power is generally considered to be lowering the operating voltage. This can either be done in a dynamic scheme according to operating conditions [8] or statically during hold cycles.…”

Section: Introductionmentioning

confidence: 99%

“…This can either be done in a dynamic scheme according to operating conditions [8] or statically during hold cycles. However, a standard 6T bitcell is limited to a minimum operating voltage of approximately 0.7 V, mainly due to process variations that degrade the read and write margins [2]. Read margin constraints are solved by using a two-port 8T bitcell, due to its decoupled readout path (for example, the circuits used in [9,10]), however write margins still limit this cell to 700 mV under global and local variations.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, many groups have developed robust bitcells, designed for low voltage and sub-threshold operation. In 2007, a 256 kb SRAM array in 65 nm with a 10T bitcell, operating under 400 mV at 475 kHz was presented by Calhoun and Chandrakasan [2] showing a 3.28 μW power consumption. In 2009, a 32 kb SRAM in 90 nm with a 10T bitcell, operating successfully at 160 mV at 500 Hz with a read power dissipation of 0.123 μW was presented by Roy's group at Purdue [11].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A Minimum Leakage Quasi-Static RAM Bitcell

Teman

Pergament

Cohen

et al. 2011

JLPEA

View full text Add to dashboard Cite

Abstract:As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.

show abstract

Section: Read Operationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Minimum Leakage Quasi-Static RAM Bitcell

Teman

Pergament

Cohen

et al. 2011

JLPEA

View full text Add to dashboard Cite

show abstract

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

Maroof

Sohail

Shin

2016

Circuit Theory & Apps

View full text Add to dashboard Cite

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre-charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre-charged to full V DD . Read port is designed such that for the read '1' operation, BL shares its charge with BLB, and for read '0' operation, BL is charged toward V DD and BLB is discharged to the ground. The proposed non-V DD BL pre-charging and the charge-sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting preamplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single-ended write driver is also presented that only conditionally charges the write BL. The proposed 10-transistor static random access memory cell using DDR provides more than 2 times read static noise margin,~72% read power savings, and~40% write power savings compared with the conventional six-transistor static random access memory. sense amplifier (SA), and write driver are shared by a column. A 6T bit cell and SA are also shown in the figure.Voltage scaling is the most effective knob for reducing power consumption. Low-voltage operation of SRAM is of keen interests to the research community. Several different SRAM cells, array architectures, and assist techniques have been proposed as the conventional 6T SRAM designs fail to operate at low voltages. A conventional eight-transistor (8T) SRAM employs two (02) more transistors per cell to decouple the internal nodes from read current path and achieves a high read static noise margin (RSNM). However, 8T offers single-ended (SE) operation, which makes sensing operation very challenging. SRAM cells like nine transistors (9T) [3] and seven transistors [4] cut off the storage nodes from read path by using isolation transistors. However, both of these use SE read operation like conventional 8T cell. Another 8T cell by Saieidi et al. [5] employs the same technique and provides the differential read scheme. Nevertheless, internal node voltages of [5] floats during the read operation are affected due to the capacitive coupling. A 9T cell by Liu and Kursun [6] and another 9T cell by Ltkemeier et al. [7] have differential read decoupled capability. A 10-transistor (10T) SRAM cell by Calhoun et al. [8] reduces the cell leakages at the cost of read speed and provides SE read operation. Another 9T cell by Wang et al. [9] uses a SE read port and provides the equalized leakage for read '0' and read '1' case.These state-of-the-art designs provide certain benefits and lack in others. For example, SEdecoupled read provides higher read stability (RSNM); nevertheless, it makes sensing operation quite challenging and power hungry. SE SRAM would require twice as much ΔV BL as does the differential scheme. However, differential read-decoupled ports either req...

show abstract

A data‐independent 9T SRAM cell with enhanced I_ON/I_OFF ratio and RBL voltage swing in near threshold and sub‐threshold region

Gupta

Pandey

2021

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary The conventional 8T SRAM cell with isolated read port is suggested as an alternative to overcome the read‐write conflicts associated with 6T SRAM cell. However, in near threshold and sub‐threshold regions, 8T cell performance is limited by reduced ION/IOFF ratio, deteriorated RBL voltage swing, data dependency, and higher read failures, although the existing SRAM cells address some of these issues but still suffer from degraded performance due to the trade‐off between leakage and read currents. In this paper, a 9T SRAM cell with novel read port is proposed that aims for low and data‐independent leakages, high ION/IOFF ratio, and large RBL voltage swing in near threshold and sub‐threshold regions. The performance of the proposed cell is compared with 7T, 8T, 9T, and 10T cells at 32 nm technology node by simulating a column of 128 cells to demonstrate its versatility over others. The proposed cell shows enhanced ION/IOFF ratio (71.2X), large RBL voltage swing and data‐independent leakages at VDD = 0.3 V in comparison to the conventional 8T SRAM cell. The results at different PVT corners are also captured to validate the impeccable performance of the proposed cell irrespective of operating conditions.

show abstract

A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

Cited by 366 publications

References 19 publications

A Minimum Leakage Quasi-Static RAM Bitcell

A Minimum Leakage Quasi-Static RAM Bitcell

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

A data‐independent 9T SRAM cell with enhanced I_ON/I_OFF ratio and RBL voltage swing in near threshold and sub‐threshold region

Contact Info

Product

Resources

About

A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

Cited by 366 publications

References 19 publications

A Minimum Leakage Quasi-Static RAM Bitcell

A Minimum Leakage Quasi-Static RAM Bitcell

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

A data‐independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub‐threshold region

Contact Info

Product

Resources

About

A data‐independent 9T SRAM cell with enhanced I_ON/I_OFF ratio and RBL voltage swing in near threshold and sub‐threshold region