A Minimum Leakage Quasi-Static RAM Bitcell

Teman, Adam; Pergament, Lidor; Cohen, Ofir; Fish, Alexander

doi:10.3390/jlpea1010204

Cited by 10 publications

(3 citation statements)

References 20 publications

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“…The proposed circuit utilizes a Supply Feedback (SF) concept that is integrated into a common latch [14]. This concept enables circuit operation throughout a wide range of supply voltages (300mV-1.1V).…”

Section: Introductionmentioning

confidence: 99%

Near-threshold 40nm Supply Feedback C-element

Schwartz

Teman

Dobkin

et al. 2011

2011 3rd Asia Symposium on Quality Electronic Design (ASQED)

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The growing demand for ultra low power applications has drawn interest in low voltage digital circuits, operating in the near-threshold region. Asynchronous circuits, operating with near-threshold supply voltages, are more attractive than their synchronous counterparts due to higher resilience to PVT variations. This paper presents a novel ultra-low power C-element, which is a basic building block in common asynchronous circuits. The proposed C-element is based on a Supply Feedback concept, implemented in a cross-coupled inverter latch. Utilization of this concept enables functionality under local and global variations down to 0.3V. The cell was designed using a standard low-power 40nm technology. Simulation results show a 5.8X-24X leakage reduction at 300mV as compared to a conventional Weak Feedback C-element operating at its minimal V DD . Monte Carlo simulations prove that the proposed cell remains fully functional under global and local process variations.

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Section: Introductionmentioning

confidence: 99%

Near-threshold 40nm Supply Feedback C-element

Schwartz

Teman

Dobkin

et al. 2011

2011 3rd Asia Symposium on Quality Electronic Design (ASQED)

Self Cite

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“…Both low voltage bitcells [11][12][13][14] and radiation hardened bitcells [9,10] have been designed, but an efficient solution covering both issues is very challenging. Recently, we proposed the SHIELD bitcell [15] specifically designed for high reliability and low-power operation.…”

Section: Introductionmentioning

confidence: 99%

A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities

Chertkow

Pescovsky

Atias

et al. 2015

JLPEA

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The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed "SEU Hardening Incorporating Extreme Low Power Bitcell Design" (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel "cut-off" network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700 mV supply voltage in a 65 nm process. To validate the bitcell's robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined.

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“…The gate dielectrics with small EOT can be obtained without the expense of an increase of the device leakage current by the employment of high- k material. The leakage current is one of the most significant issues related to device reliability [ 5 , 6 , 7 , 8 , 9 ]. Therefore, a number of high- k materials, HfO 2 , ZrO 2 , Y 2 O 3 and their silicates, have been widely studied due to their high dielectric constants [ 10 , 11 ].…”

Section: Introductionmentioning

confidence: 99%

Hysteresis in Lanthanide Zirconium Oxides Observed Using a Pulse CV Technique and including the Effect of High Temperature Annealing

Zhao

et al. 2015

Materials

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A powerful characterization technique, pulse capacitance-voltage (CV) technique, was used to investigate oxide traps before and after annealing for lanthanide zirconium oxide thin films deposited on n-type Si (111) substrates at 300 °C by liquid injection Atomic Layer Deposition (ALD). The results indicated that: (1) more traps were observed compared to the conventional capacitance-voltage characterization method in LaZrOx; (2) the time-dependent trapping/de-trapping was influenced by the edge time, width and peak-to-peak voltage of a gate voltage pulse. Post deposition annealing was performed at 700 °C, 800 °C and 900 °C in N2 ambient for 15 s to the samples with 200 ALD cycles. The effect of the high temperature annealing on oxide traps and leakage current were subsequently explored. It showed that more traps were generated after annealing with the trap density increasing from 1.41 × 1012 cm−2 for as-deposited sample to 4.55 × 1012 cm−2 for the 800 °C annealed one. In addition, the leakage current density increase from about 10−6 A/cm2 at Vg = +0.5 V for the as-deposited sample to 10−3 A/cm2 at Vg = +0.5 V for the 900 °C annealed one.

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A Minimum Leakage Quasi-Static RAM Bitcell

Cited by 10 publications

References 20 publications

Near-threshold 40nm Supply Feedback C-element

Near-threshold 40nm Supply Feedback C-element

A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities

Hysteresis in Lanthanide Zirconium Oxides Observed Using a Pulse CV Technique and including the Effect of High Temperature Annealing

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