A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities

Abstract

The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed "SEU Hardening Incorporating Extreme Low Power Bitcell Design" (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel "cut-off" network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700 mV supply voltage in a 65 nm process. To validate the bitcell's robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined.

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

“…Using dual node feedback control provides full SEU fault immunity, however, cannot fully tolerate multiple node upsets because of negative effects of charge sharing induced by particle strikes [9], [11]. Furthermore, the area overhead, power consumption and delay are high compared to the conventional 6T SRAM cell [10], [13], [12]. Especially its high area overhead restricts the applicability where area efficiency is essential [9].…”

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

“…So far, various differential (dual) and single bitline radiation hardened SRAM cells have been published by researchers which can tolerate SNUs and MNUs, in typical types (based on basic structure in radiation hardened memory cells such as dual interlocked storage cell (DICE), 11 Quatro, 12 ), terrestrial (low-orbit) and aerospace (highorbit) applications using RHDB and layout approaches. [13][14][15][16][17][18][19][20][21][22][23][24][25] In the literature, 19,20 some asymmetrical hardened SRAM cells, where some symmetrical bitline hardened SRAM cells in literatures, [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21] are proposed. Also, single bitline (or single-ended) hardened SRAM cells based on Muller C-elements are proposed in referances.…”

“…Also, single bitline (or single-ended) hardened SRAM cells based on Muller C-elements are proposed in referances. 22,23 In the literature, 24,25 based on RHBD combined with a layout-level technique, the radiation hardening memory cells with self-recover approach from any SNU, any double-adjacent-node upsets (DANUs) and partial double-separated-node upsets (DSNUs) has been proposed. However, SRAM structures based on RHBD still have disadvantages, which are as follows:…”

“…(1) Most of the existing SRAM cells cannot self-recover from all possible SNU (anti-SNU), since one or more nodes cannot tolerate SNUs. 12,[17][18][19][20]22,23 Moreover, some radiation hardened (rad-hard) memory bit-cells cannot be a part of DNUs. 11,12,19,20,22 (2) Most of the existing hardened bit-cells suffer from a large overhead especially in terms of silicon area and/or power dissipation.…”

“…Moreover, some memory bit-cells suffer from a large write-and read-access time. 19,22,23 (3) Some SRAM architectures in literature, 20,24,25 have used layoutbased design solutions to any DUNs tolerance as well as any SUN, but this technique can increase the complexity of memory cell designs.…”