A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers

Nagaraj, K.; Fetterman, H.S.; Anidjar, J.; Lewis, S.H.; Renninger, R.G.

doi:10.1109/4.557628

Cited by 166 publications

(50 citation statements)

References 21 publications

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“…This allows us to compress two stages of the pipeline architecture into one basic building block containing a single opamp and several capacitors. The process of opamp sharing [27] [28] stems from the use of global offset chopping and leads to power and some area savings. Additionally, global offset compensation is far simpler to implement than doing opamp offset correction at a local opamp level.…”

Section: Advantages Of Global Adc Offset Cancellationmentioning

confidence: 99%

A low-power reconfigurable analog-to-digital converter

Gulati

Lee

2001

IEEE J. Solid-State Circuits

100

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This thesis presents the concept, theory and design of a low power CMOS analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption. The converter achieves the wide operating range by reconfiguring (1) its architecture between pipeline and delta-sigma modes (2) by varying its circuit parameters such as size of capacitors, length of pipeline, oversampling ratio, among others and (3) by varying the bias currents of the opamps in proportion with converter sampling frequency, accomplished through the use of a phase-locked loop. Target input signals for this ADC include high frequency and moderate resolution signals such as video and low I.F. in radio Receivers, low frequency and high resolution signals from seismic sensors and MEMs devices, and others that fall in between these extremes such as audio, voice and general purpose data-acquisition. This converter also incorporates several power reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design.At a converter power supply at 3.3V, the converter achieves a bandwidth range of 0-10MHz over a resolution range of 6 -16 bits, and parameter reconfiguration time of 12 clock cycles. Its PLL lock range is measured at 20KHz to 40MHz. In the delta-sigma mode, it achieves a maximum SNR of 94dB and second and third harmonic distortions of 102dB and 95dB, respectively at 10MHz clock frequency, 9.4KHz bandwidth, and 17.6mW power. In the pipeline mode, it achieves a maximum DNL and INL of +/-0.55LSBs and +/-0. 82LSBs, respectively, at 11-bits of resolution, at a clock frequency of 2.6MHz and 1MHz tone with 24.6mW of power.

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Section: Advantages Of Global Adc Offset Cancellationmentioning

confidence: 99%

A low-power reconfigurable analog-to-digital converter

Gulati

Lee

2001

IEEE J. Solid-State Circuits

100

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“…Due to the finite gain of the opamp a fraction of the previous sample remains stored in the parasitic capacitance in the input of the amplifier [96,186]. Using the z-transform the voltage gain of the circuit in Figure 9.3 can be written as…”

Section: Memory Effectmentioning

confidence: 99%

“…Since then several two-channel parallel pipeline ADCs have been published: e.g. [95,96,97,98,99,100,101,102]. The implementation of a four-channel prototype, originally published in [4], will be described in Section 12.4.…”

Section: Time-interleaved Adcmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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“…We use the input-output transfer characteristic of the MDAC, also known as the residue transfer curve for our discussion. The scheme presented here is similar to that discussed in [6], [7] for the design of a 3-level MDAC with 1 bit of digital redundancy. The scheme involves halving the SHA gain G and leaving out 1 comparator threshold.…”

Section: B Example: 5-level Mdacmentioning

confidence: 87%

A Generic Multilevel Multiplying D/A Converter for Pipelined ADCs

Sharma

Moon

Temes

2005 IEEE International Symposium on Circuits and Systems

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Abstract-State-of-art implementations of pipelined ADCs can only realize a multiplying DAC (MDAC) with (2 n -1) levels. However, the number of levels needed to optimize the performance may differ from this number. A novel scheme is proposed allowing for realization of an arbitrary number of MDAC levels, while allowing for 1 bit of digital redundancy and digital error correction without any overhead.

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A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers

Cited by 166 publications

References 21 publications

A low-power reconfigurable analog-to-digital converter

A low-power reconfigurable analog-to-digital converter

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

A Generic Multilevel Multiplying D/A Converter for Pipelined ADCs

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