A low-power reconfigurable analog-to-digital converter

Gulati, Kush; Lee, Hae-Seung

doi:10.1109/4.972140

Cited by 100 publications

(11 citation statements)

References 18 publications

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“…Many ADC architectures have traditionally relied upon the use of op-amps, including pipeline and delta-sigma ADCs. In [73], a reconfigurable, op-amp based ADC is presented that can switch between pipeline and deltasigma modes. The converter achieves a bandwidth range of 0-10 MHz and a resolution range of 6-16 bits.…”

Section: A Reconfigurable Adc Techniquesmentioning

confidence: 99%

Technologies for Ultradynamic Voltage Scaling

et al. 2010

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Circuits such as logic cells, static random access memories, analog-digital converters and dc-dc converters can be used as building blocks for applications that can function efficiently over a wide range of supply voltages.ABSTRACT | Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multimedia to biomedical monitoring. An added challenge is that many of these applications have dynamic workloads. To reduce the energy consumption under these variable computation requirements, the underlying circuits must function efficiently over a wide range of supply voltages. This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc-dc converters. Using these circuits as building blocks, two different applications are highlighted. First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V. Second, we describe a 0.3 V 16-bit microcontroller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc-dc converter. Fig. 5. Trend in minimum energy point of a 32 b adder with process scaling using predictive models [31].

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Section: A Reconfigurable Adc Techniquesmentioning

confidence: 99%

Technologies for Ultradynamic Voltage Scaling

et al. 2010

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“…A reconfigurable ADC can cope with many of these signals while minimizing area and power in the corresponding readout system. This component must be able to satisfy different resolution and bandwidth requirements, keeping a minimum and constant figure-of-merit (FoM) in each mode of operation [5]. In this paper, FoM is calculated as in [6]:…”

Section: Introductionmentioning

confidence: 99%

A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

Porrazzo

Morgado

Bello

et al. 2014

Circuit Theory & Apps

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SUMMARYThis paper presents a methodology to design reconfigurable switched-capacitor (SC) delta-sigma modulators Ms) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for lowbandwidth, medium-to-high resolution specifications, which are common in bio-medical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class-A and class-AB OTAs is presented. The power-optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution or program all sampling capacitors to the required resolution. The second approach results in the best trade-off between power efficiency and simplicity. A reconfigurable ΔΣM for bio-medical applications is designed at transistor-level in a 0.18μm CMOS process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%; validating thus the proposed approach.

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“…For this reason there have been some proposals for configurable analog circuits [4] and software radio circuits [5]. Importantly, such circuits can be pre-characterized for the subtle device properties and coupling parasitics that are difficult to predict prior to layout and manufacturing.…”

Section: Introductionmentioning

confidence: 99%

Oracle

Pileggi

Boyd

2004

Proceedings of the 41st Annual Design Automation Conference

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Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for technologies below 100nm, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support full custom implementation. Design reuse and analog synthesis make analog/RF design more affordable; however, the increasing process variability and lack of modeling accuracy remains extremely challenging for nanoscale analog/RF design. We propose an analog/RF circuit design methodology ORACLE, which is a combination of reuse and shared-use by formulating the synthesis problem as an optimization with recourse problem. Using a two-stage geometric programming with recourse approach, ORA-CLE solves for both the globally optimal shared and applicationspecific variables. Concurrently, we demonstrate ORACLE for novel metal-mask configurable designs, where a range of applications share common underlying structure and application-specific customization is performed using the metal-mask layers. We also include the silicon validation of the metal-mask configurable designs.

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A low-power reconfigurable analog-to-digital converter

Cited by 100 publications

References 18 publications

Technologies for Ultradynamic Voltage Scaling

Technologies for Ultradynamic Voltage Scaling

A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

Oracle

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