A 250- $\mu\text{W}$ 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications

Hong, Seungbum; Kim, Shinwoong; Choi, Sung‐Min; Cho, Hwasuk; Hong, Jaehyeong; Seo, Young Hun; Kim, Byungsub; Park, Hong-June; Sim, Jae‐Yoon

doi:10.1109/tcsii.2016.2551598

Cited by 8 publications

(3 citation statements)

References 14 publications

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“…Note that although we used a relatively high reference frequency for faster lock in, we still achieved sub-mW power consumption. The jitter is acceptable to most applications that require less precise clock generation, and comparable with [31] and [32]. Thanks to the sub-mW power consumption, our PWPLL realizes competitive FoM compared to the prior works.…”

Section: Measurement Resultsmentioning

confidence: 93%

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool

Wang

Iizuka

et al. 2019

IEICE Electron. Express

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This paper demonstrates the design flow of a quick-start pulsewidth-controlled PLL with automated layout synthesis using a place-androute tool. The quick-start PWPLL converts the internal state into an analog-digital mixed signal called soft-thermometer-code (STC) and stores them into memory before PWPLL is turned off in order to enhance the start-up in the next turn-on. Our chip fabricated with TSMC 65 nm shows 220 ns settling time (13 reference clock cycles), 858 µW power consumption under 1 V nominal supply voltage with 59 µm × 58 µm silicon area. The measurement results demonstrate that the design-automated PLL realizes the FoM of −221.7 dB, which is roughly the same value as that of the manually-designed one with the same target specification.

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Section: Measurement Resultsmentioning

confidence: 93%

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool

Wang

Iizuka

et al. 2019

IEICE Electron. Express

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show abstract

“…Ideally, the locking time should be as small as possible. The traditional structure All-Digital Phased Locked Loop (TS-ADPLL) usually uses the adaptive-bandwidth technique [5] or the Digitally Controlled Oscillator (DCO) tuning word estimating with presetting technique [6][7][8] to reduce the locking time. The adaptive-bandwidth technique changes the bandwidth of filter according to the different state.…”

Section: Introductionmentioning

confidence: 99%

A Novel Fast-Locking ADPLL Based on Bisection Method

Deng

Zhu

2021

Electronics

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Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.

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“…The output clock frequency is set by the divider ratio and a sigma delta modulator (SDM) is used to dither the divider ratio between two integer values to achieve a fractional division ratio. Figure 2.30 shows a proposed master-slave ADPLL architecture [72] for reducing power consumption. The proposed architecture consists of a master PLL producing a low frequency which is followed by a high output frequency slave injection-locked oscillator.…”

Section: Divider-less Adpllmentioning

confidence: 99%

Investigation and design of low power circuit blocks for medical implant SOCs

Arjun¹

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A 250- $\mu\text{W}$ 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications

Cited by 8 publications

References 14 publications

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool

A Novel Fast-Locking ADPLL Based on Bisection Method

Investigation and design of low power circuit blocks for medical implant SOCs

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