A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical Interconnects

Chujo, Norio; Takai, Toshiaki; Sugawara, Toshiki; Matsuoka, Y.; Kawamura, D.; Adachi, K.; Kawamata, Tsuneo; Ohno, Toshinobu; Ohhata, Kenichi

doi:10.1109/tcsi.2011.2163982

Cited by 16 publications

(5 citation statements)

References 11 publications

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“…Transistors can be stacked to reach multiples of breakdown voltages. This is a technique common for drivers in CMOS such as [22], [23], or [24]. However, this technique is sensitive to start-up sequences and might breakdown on transient peaks.…”

Section: Design Of the Laser Diode Drivermentioning

confidence: 99%

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

Szilágyi

Belfiore

Henker

et al. 2017

Int. J. Microw. Wireless Technol.

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The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm2, is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10−12at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.

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Section: Design Of the Laser Diode Drivermentioning

confidence: 99%

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

Szilágyi

Belfiore

Henker

et al. 2017

Int. J. Microw. Wireless Technol.

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show abstract

“…In pHEMT technology, a 10 Gbps modulator driver with 1.8 V pp single-ended output voltage and a 100 mA 10 Gbps laser driver with active back termination were proposed in Refs. [15,9], respectively. On the other hand, the CMOS process can still compete to implement such circuits using broadband techniques like inductive peaking [3, 5, 12, 16−18] and negative impedance converters [4,12,19] .…”

Section: Introductionmentioning

confidence: 99%

A 15 Gbps-NRZ, 30 Gbps-PAM4, 120 mA laser diode driver implemented in 0.15-µm GaAs E-mode pHEMT technology

2021

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This paper presents the design and testing of a 15 Gbps non-return-to-zero (NRZ), 30 Gbps 4-level pulse amplitude modulation (PAM4) configurable laser diode driver (LDD) implemented in 0.15-µm GaAs E-mode pHEMT technology. The driver bandwidth is enhanced by utilizing cross-coupled neutralization capacitors across the output stage. The output transmission-line back-termination, which absorbs signal reflections from the imperfectly matched load, is performed passively with on-chip 50-Ω resistors. The proposed 30 Gbps PAM4 LDD is implemented by combining two 15 Gbps-NRZ LDDs, as the high and low amplification paths, to generate PAM4 output current signal with levels of 0, 40, 80, and 120 mA when driving 25-Ω lasers. The high and low amplification paths can be used separately or simultaneously as a 15 Gbps-NRZ LDD. The measurement results show clear output eye diagrams at speeds of up to 15 and 30 Gbps for the NRZ and PAM4 drivers, respectively. At a maximum output current of 120 mA, the driver consumes 1.228 W from a single supply voltage of –5.2 V. The proposed driver shows a high current driving capability with a better output power to power dissipation ratio, which makes it suitable for driving high current distributed feedback (DFB) lasers. The chip occupies a total area of 0.7 × 1.3 mm2.

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“…Introduction: Development of information technology constantly increases the demand for interconnects with extremely high data rates. The dramatic increases of connection density introduces challenges due to power consumption issues and electromagnetic interferences [1]. On one hand, technology scaling reduces mass production costs, power consumption and increases the computational performance of the core circuits.…”

mentioning

confidence: 99%

Common cathode VCSEL driver in 90 nm CMOS enabling 25 Gbit/s optical connection using 14 Gbit/s 850 nm VCSEL

et al. 2015

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The design and electro-optical measurements of a 25 Gbit/s common cathode vertical cavity surface-emitting laser (VCSEL) driver in 90 nm bulk CMOS technology is presented. The driver is bonded to a 14 Gbit/s commercial VCSEL providing both DC and modulation current to the laser. The power consumption including the VCSEL is 60 mW. Since the DC bias of the VCSEL exceeds the breakdown voltage of thin oxide transistors, a novel output stage configuration using isolated wells is proposed. The active area is only 127 × 50 μm.Introduction: Development of information technology constantly increases the demand for interconnects with extremely high data rates. The dramatic increases of connection density introduces challenges due to power consumption issues and electromagnetic interferences [1]. On one hand, technology scaling reduces mass production costs, power consumption and increases the computational performance of the core circuits. On the other hand, inter-chip electrical connections continue to be restricted by the physical limits of the electrical channels [2]. One possible solution is the use of power-efficient optical interconnects as their frequency-dependent loss is negligible; they allow a high data rate and they are not affected by electrical crosstalk [3]. A costefficient implementation of these links is the use of a directly modulated vertical cavity surface-emitting laser (VCSEL) controlled by a driver circuit in a low-cost CMOS technology. In this case, the laser driver can be integrated in one system with the core chip, thus avoiding multichip packaging costs and performance deterioration. The commercial availability of more than 25 Gbit/s VCSELs is increasing, their power dissipation and costs are low and VCSELs are good candidates for the implementation of low-power optical interconnects [3]. One of the fastest available VCSELs to date has a bandwidth of 26 GHz [4]. Since VCSELs emit light vertically, with two-dimensional arrays multiple parallel 25 Gbit/s optical channels can be realised [5] as defined in the future Ethernet Standard 802.3bs. This Letter presents a practical implementation and the measurement results of a low-power, high-speed common cathode VCSEL driver in CMOS technology. The driver is very compact and can be easily integrated with the serialiser and re-timer circuit removing the 50 Ω input resistance used only for the measurement purposes.

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A 25 Gb/s 65-nm CMOS Low-Power Laser Diode Driver With Mutually Coupled Peaking Inductors for Optical Interconnects

Cited by 16 publications

References 11 publications

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

A 15 Gbps-NRZ, 30 Gbps-PAM4, 120 mA laser diode driver implemented in 0.15-µm GaAs E-mode pHEMT technology

Common cathode VCSEL driver in 90 nm CMOS enabling 25 Gbit/s optical connection using 14 Gbit/s 850 nm VCSEL

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