A 25.1 dBm 25.9-dB Gain 25.4% PAE X-band Power Amplifier Utilizing Voltage Combining Transformer in 65-nm CMOS

Trinh, Van‐Son; Park, Jung‐Dong

doi:10.1109/access.2020.3048757

Cited by 13 publications

(7 citation statements)

References 33 publications

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“…Push-pull amplifiers have been widely used in PA design due to their compactness, high efficiency, and high-power performances [ 29 , 30 ]. Since the load of the first buffer stage also affects the tuning range of the VCO, the active device size of the first stage should be restricted to keep a reasonable tuning range of the VCO.…”

Section: W-band Cross-coupled Vco Designmentioning

confidence: 99%

“…The two-stage buffer structure also enhances the isolation between the CCP and output of the VCO, mitigating the pulling effect of the CCP core from the load variation. It is well-conceived that the differential pair of active devices constructed by two common source amplifiers is conditionally unstable due to the gate-to-drain parasitic capacitor C gd of the transistors [ 29 ]. Regarding the first buffer stage, it is possible to allow it to be conditionally unstable with a stability factor smaller than unity since its input resistance generated by the cross-coupled pair is inherently negative.…”

Section: W-band Cross-coupled Vco Designmentioning

confidence: 99%

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A 78.8–84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS

Trinh¹,

Nam²,

Song³

et al. 2022

Sensors

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A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.

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Section: W-band Cross-coupled Vco Designmentioning

confidence: 99%

Section: W-band Cross-coupled Vco Designmentioning

confidence: 99%

A 78.8–84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS

Trinh¹,

Nam²,

Song³

et al. 2022

Sensors

Self Cite

View full text Add to dashboard Cite

show abstract

“…The value of the neutralization capacitor is chosen to be roughly Cgd of the transistor [7]. Specifically, Rollet's stability factor (K-Δ) and the maximum stable gain (Gma) values of the amplifier were investigated carefully to ensure its stable operation [8].…”

Section: Millimeter-wave Push-pull Pa Designmentioning

confidence: 99%

“…The gate bias voltage (VGS) for the three stages was chosen considering the trade-offs between the dc-power dissipation and the maximum output power. The VGS for the output stage (3 rd ) was chosen to be 0.7 V to achieve a good output power while the VGS for the input and the driving stages was chosen to be 0.6 V for the better power gain [8].…”

Section: Millimeter-wave Push-pull Pa Designmentioning

confidence: 99%

A 16.4-dBm 20.3% PAE 22-dB Gain 77 GHz Power Amplifier in 65-nm CMOS Technology

Trinh

Park²

2021

IEEE Access

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We present a compact W-band power amplifier (PA) for automotive radar application in 65nm CMOS technology. The circuit adopts a pseudo-differential push-pull configuration based on transformers (TFs) which offer highly efficient and flexible matching networks with minimized area occupancy. We have set the optimal output resistance close to 50 Ω, design guidelines in sizing active devices for each stage, and the corresponding transformers were presented for optimal power efficiency based on an analysis of surrounding matching networks. Working under a supply voltage of 1.3-V, the implemented 77GHz PA achieved a 3-dB gain bandwidth of 9-GHz (72.5-81.5 GHz), a peak gain of 22.4 dB, a saturated power (Psat) of 16.4 dBm, and a peak power-added efficiency (PAE) of 20.3%. The area for the core layout is only 0.05 mm 2 , which demonstrates the highest power density among the recently reported W-band CMOS PAs.

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“…Transformers are often heavy components and are not recommended for portable systems. Multistage PAs, such as [4,5] with Series structures in several stages amplify the signal and ultimately increase the gain and efficiency. In Series structures, the design of appropriate matching networks between each stage increased the complexity of the circuit and made it difficult for the designer.…”

Section: Introductionmentioning

confidence: 99%

A Wide-Band High-Gain Doherty Power Amplifier With Class-AB HEMT Amplifiers

Jahanian

Kangarshahi

2021

Preprint

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In this paper, an attempt has been made to design a Doherty power amplifier (DPA) with high-gain and wide-band. For this purpose, two peak amplifiers are used to improve the performance of the main amplifier. Main and auxiliary amplifiers with the same structure to the class-AB type and by using micro-strip lines in place of input/output and load matching networks, transmission lines and inductors of drain and gate, that minimize the losses in the DPA. The current DPA is implemented with GaN_HEMT_CLF1G0530_100v transistor and Rogers4003 substrate, which for 1GHz frequency in 0.5-1.5GHz bandwidth will be able to be at P-1dB point (this point, input power as 30dBm and output power as 47.98dBm) increase Drain efficiency and Power added efficiency (PAE) to 81.95% and 80.73%, respectively. The DPA helps to expand the back-off region and extend the linearity region, so the Peak to average power ratio (PAPR) will be 5.21dB and the Adjacent channel power ratio (ACPR) as 58.7dBc. A gain of 17.06-17.92dB was also obtained, which is significant compared to the results of similar samples.

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A 25.1 dBm 25.9-dB Gain 25.4% PAE X-band Power Amplifier Utilizing Voltage Combining Transformer in 65-nm CMOS

Cited by 13 publications

References 33 publications

A 78.8–84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS

A 78.8–84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS

A 16.4-dBm 20.3% PAE 22-dB Gain 77 GHz Power Amplifier in 65-nm CMOS Technology

A Wide-Band High-Gain Doherty Power Amplifier With Class-AB HEMT Amplifiers

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