A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth

Theertham, Raviteja; Koottala, Prasanth; Billa, Sujith; Pavan, Shanthi

doi:10.23919/vlsic.2019.8778026

Cited by 8 publications

(3 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the sensor and industrial frequency range, we can then highlight a few further designs. First, Theertham et al [132] implemented again a CT ADC employing an FIR DAC and chopping, where the chopping artifacts advantageously fall into the FIR notches, as also originally proposed in [130]. Also, this design is implemented in a mature 180-nm technology.…”

Section: ) Techniques For Narrowband Adcsmentioning

confidence: 99%

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Jang,

Tang,

Lim

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

View full text Add to dashboard Cite

The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.INDEX TERMS Analog-to-digital converter (ADC), continuous-time (CT), delta-sigma modulation, energy efficient, low power, noise-shaping (NS), pipelining, successive approximation.

show abstract

Section: ) Techniques For Narrowband Adcsmentioning

confidence: 99%

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Jang,

Tang,

Lim

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

View full text Add to dashboard Cite

show abstract

“…To avoid instability due to the extra delay introduced by the FIR-DAC, a compensation FIR-DAC is connected to the output of the first stage. The k i coefficients [0, 0.87, 0.75, 0.62, 0.5, 0.37, 0.25, 0.12] are chosen to make the sampled impulse response of the resulting loop filter the same as that of an integrator driven by a 1-bit DAC [10].…”

Section: Readout Circuitrymentioning

confidence: 99%

“…However, due to the CT front-end, the chopping frequency f CHOP should be set to f S /2 or f S to avoid quantization noise-folding, which happens at 2f CHOP . Conveniently, the equally weighted 8-tap FIR-DAC creates notches in the modulator's noise transfer function (NTF), which allows f CHOP to be safely set to multiples of f S /2Nt, where Nt is the number of taps [10]. The CCIA and the integrator are chopped in this design at f CH4K = f S /8 and f CH2K = f S /16, respectively.…”

Section: Readout Circuitrymentioning

confidence: 99%

A 2.5-µW Beyond-the-Rails Current Sensor With a Tunable Voltage Reference and ±0.6% Gain Error From −40 °C to +85 °C

Zamparette

Makinwa

2022

IEEE Solid-State Circuits Lett.

View full text Add to dashboard Cite

This letter presents a low-power, fully integrated current sensor for Coulomb-counting. It employs a hybrid delta-sigma modulator ( M) with an FIR-DAC to digitize the voltage drop across a shunt. The modulator's first stage consists of a capacitively coupled chopper amplifier, which enables a beyond-the-rails (−0.3 to 5 V) input commonmode voltage range from a 1.8-V supply. A tunable voltage reference is used to accurately compensate for the large temperature coefficient (∼3500 ppm/ • C) of low-cost metal shunts. With a 20-m on-chip shunt, ±2 A currents can be digitized with 0.35% gain error from −40 • C to 85 • C, after a 1-point trim. With a 3-m PCB trace, currents up to ±15 A can be digitized with 0.6% gain error over the same temperature range. Fabricated in a standard 0.18-μm CMOS process, the sensor occupies 1.6 mm 2 and consumes 2.5 μW, which is 3× less than the state of the art. It also achieves competitive energy efficiency, with a figure of merit (FoM) of 149 dB.

show abstract

Continuous-Time Delta-Sigma Converters with Finite-Impulse-Response (FIR) Feedback

Pavan

2019

Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits

View full text Add to dashboard Cite

A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth

Cited by 8 publications

References 2 publications

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Design Techniques for Energy-Efficient Analog-to-Digital Converters

A 2.5-µW Beyond-the-Rails Current Sensor With a Tunable Voltage Reference and ±0.6% Gain Error From −40 °C to +85 °C

Continuous-Time Delta-Sigma Converters with Finite-Impulse-Response (FIR) Feedback

Contact Info

Product

Resources

About