Design Techniques for Energy-Efficient Analog-to-Digital Converters

Abstract

The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.INDEX TERMS Analog-to-digital converter (ADC), continuous-time (CT), delta-sigma modulation, energy efficient, low power, noise-shaping (NS), pipelining, successive approximation.

Side-Channel Attacks on Analog-to-Digital Converters: A Survey and Comparison with Cryptos

“…Among oversampling ADCs, ∆Σ, Multi-stage Noise Shaping (MASH), and Continuoustime ∆Σ architectures are available [56]. Beyond the two conventional ADC categories, the latest trends in ADC include Noise-shaping SAR ADCs [57]- [59], incremental ADCs [60], [61], and time-domain techniques [62]. The vulnerability of these other ADC topologies is a wide-open question.…”