A 21-mW 4-Mb CMOS SRAM for battery operation

Murakami, Shuji; Fujita, Katsushi; Ukita, M.; Tsutsumi, K.; Inoue, Yasuo; Sakamoto, O.; Ashida, M.; Nishimura, Yasumasa; Kohno, Y.; Nishimura, Tadashi; Anami, Keiko

doi:10.1109/4.98973

Cited by 16 publications

(2 citation statements)

References 14 publications

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“…There are three types of memory cell, all of which operate as flip-flops, used in the SRAM which is currently in production. Besides the mainstream CMOS type [1], there are a high-resistance load type [2] and a TFT (thin film transistor) load type [3]. In general, the CMOS type is regarded to be superior in terms of both its standby current properties and low-voltage operation properties.…”

Section: Prior Art and Issuesmentioning

confidence: 99%

A new type of SRAM using DRAM technology

Kihara

Okamura

Nakashima

et al. 2007

Electron Comm Jpn Pt II

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SUMMARY16-Mbit low-power SRAM (SuperSRAM) was developed using a new memory cell technology which makes use of DRAM technology and TFT technology, which has a record of actual performance in SRAM. For SRAM, the problems of soft errors and operation at the lower limits of V cc have manifested at the increasing levels of miniaturization, and increases in capacity have become increasingly difficult. Nonetheless, complete compatibility with asynchronous SRAM has been implemented with the free use of circuit technology, while various problems have been resolved without cost increases using DRAM memory cell technology, which reduces surface area. The characteristics of such devices are discussed predominantly from the perspective of design.

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Section: Prior Art and Issuesmentioning

confidence: 99%

A new type of SRAM using DRAM technology

Kihara

Okamura

Nakashima

et al. 2007

Electron Comm Jpn Pt II

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“…Traditionally, the bitline swings during a read access have been limited by using active loads of either diode-connected nMOS or resistive pMOS [10], [11], but these clamp the bitline swing at the expense of a steady bitline current. A more powerefficient way of limiting the bitline swings is to use high-impedance bitline loads and pulse the wordlines [12]- [15].…”

Section: Introductionmentioning

confidence: 99%

A replica technique for wordline and sense control in low-power SRAM's

Amrutur¹,

Horowitz²

1998

IEEE J. Solid-State Circuits

166

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With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications of SRAM's. We present techniques based on replica circuits which minimize the effect of operating conditions' variability on the speed and power. Replica memory cells and bitlines are used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulsewidths to limit bitline swings. We implemented the circuits for two variants of the technique, one using bitline capacitance ratioing in a 1.2-m 8-kbyte SRAM, and the other using cell current ratioing in a 0.35m 2-kbyte SRAM. Both the RAM's were measured to operate over a wide range of supply voltages, with the latter dissipating 3.6 mW at 150 MHz at 1 V and 5.2 W at 980 kHz at 0.4 V.

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Low-Power CMOS Random Access Memory Circuits

Bellaouar

Elmasry

1995

Low-Power Digital VLSI Design

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A 21-mW 4-Mb CMOS SRAM for battery operation

Cited by 16 publications

References 14 publications

A new type of SRAM using DRAM technology

A new type of SRAM using DRAM technology

A replica technique for wordline and sense control in low-power SRAM's

Low-Power CMOS Random Access Memory Circuits

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