Low-Power CMOS Random Access Memory Circuits

Bellaouar, A.; Elmasry, M.I.

doi:10.1007/978-1-4615-2355-0_6

Low-Power Digital VLSI Design 1995

DOI: 10.1007/978-1-4615-2355-0_6

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Low-Power CMOS Random Access Memory Circuits

A. Bellaouar

M.I. Elmasry

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2021

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Soft Error-Resilient RHBD16T SRAM Cell in 32nm Technology

Kaushal

Murgan²,

Pattanaik

et al. 2021

Advances in Computer and Electrical Engineering

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Radiation environment generates high soft error rates in conventional SRAM. To overcome this issue, several radiation hardened by design SRAM circuits (12TRHBD, 13TRHBD, DICE, etc.) have been developed. Although many of the radiation hardened SRAM cells are there, all the circuits mainly concern a single node upset only. In this chapter, 16T radiation hardened static random-access memory bit cell is designed and verified for a single node and multi-node upset. RHBD 16T bit cell is designed with SAED-PDK 32nm technology and compared with recently reported RHBD 12T and has a 99% improvement in recovery rate. Simulation results show that RHBD 16T is more resilient to a single node and multi-node upset. This shows that the proposed RHBD16T cell is highly tolerant against radiation strikes.

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Soft Error-Resilient RHBD16T SRAM Cell in 32nm Technology

Kaushal

Murgan²,

Pattanaik

et al. 2021

Advances in Computer and Electrical Engineering

View full text Add to dashboard Cite

show abstract

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Low-Power CMOS Random Access Memory Circuits

Cited by 1 publication

References 48 publications

Soft Error-Resilient RHBD16T SRAM Cell in 32nm Technology

Soft Error-Resilient RHBD16T SRAM Cell in 32nm Technology

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