A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications

Abstract

This work presents a 21.7-to-27.8GHz frequency synthesizer in a 45nm CMOS process that combines a tuning range of 24.8%, a residual phase modulation of 2.57°rms (with integrated phase noise from 100kHz to 100MHz), and a total power dissipation of 40mW. Combined with a frequency multiplier-by-two circuit and a divider-by-two circuit in a sliding-IF configuration, the PLL provides the four source frequencies required by the IEEE 802.15.3c 60GHz communication standard. In addition, the attained phase noise makes it suitable for microwave links with higher-order modulation schemes used as the back-bone for 3G/LTE base-station networks.The PLL diagram is shown in Fig. 16.1.1. It consists of a PFD supplied by a 1.1V source, a programmable charge pump (CP) supplied with 1.8V, an external loop filter, a negative-g m VCO, a fixed prescaler, a chain of 2/3-dividers and two buffers.The VCO diagram is shown in Fig. 16.1.2; it is a cross-coupled pair oscillator with AC coupling in the feedback network. The variable capacitance is composed of a thin-oxide accumulation-mode varactor and three binary-weighted programmable capacitors. The thin-oxide varactor has a better Q and gives a larger tuning range than a thick-oxide varactor. To cope with the low breakdown the drain of the cross-coupled VCO is biased at 0.9V and a control signal from 0 to 1.8V is used. This provides large tuning range and optimal phase-noise performance simultaneously. The VCO draws a maximum current of 13.5mA from a 0.9V supply. Two buffers are used to drive a 100Ω differential output and the divider. They consume a total of 7mA from the 1.1V supply.The inset in Fig. 16.1.2 demonstrates the locking range of the PLL for every band of the VCO. It also shows the four frequencies needed, with the sliding-IF scheme mentioned above, to fulfill the standard.The divider chain is composed of one divider-by-two followed by a programmable multi-modulus divider based on a chain of 2/3-divider cells, see Fig. 16.1.1. The last 2/3-divider can be disabled to reduce the lowest division ratio [1]. The division range spans from 256 to 1022 in steps of two. The divider-by-two and the first two 2/3-dividers are implemented using CML, in contrast with the Injection-Locked Frequency Dividers (ILFD) used in some of the previous comparable CMOS PLL's [2,3]. The CML approach increases the robustness of the divider chain, as it is inherently broadband, and does not require calibration or tracking schemes to increase the operation range. The last 7 divider cells use Swing-Restored Pass-Transistor Logic (SRPT) and consume 400μW operating at 3.48GHz from the 1.1V supply.In Fig. 16.1.3 the architecture of the first 2/3-divider cell is shown, together with one of the latches. The divider input signal is AC-coupled to obtain the 0.75mV optimum DC level that results in maximum speed for an implementation using low-V t transistors. The first two 2/3-divider cells were measured stand-alone, with a 50-Ω input buffer, showing a maximum operating frequency of 18GHz and a self-oscillation freq...

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

“…[8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. 4 GHz, with margin, meeting requirements for a 60-GHz superheterodyne radio [2].…”

Phase noise suppression techniques for high frequency synthesizers in 65 nm CMOS

“…is PLL phase noise, t calculation of reference [1,2,3,4,5] uses the data in their phase noise measurement results.…”

“…As a result, 0.3 V (red curve) is the best choice of V bias for tuning range extension. It is improper in wide band design to connect varactors to LC tank directly like in [3,4], because tank DC voltage is V DD for the proposed topology, and the corresponding capacitance range is too small.…”

“…Several implementations of high frequency PLL with techniques to improve the phase noise performance have been reported recently [1,2,3,4,5]. The first design challenge to implement high frequency PLL is integrating a wide tuning range low phase noise voltage-controlled oscillator (VCO) which determines the PLL out-ofband phase noise.…”

“…Section 2 describes the circuit implementation of the proposed X-band PLL design. Section 3 discusses the advantages of the proposed phase noise suppression techniques with experimental results and offers a comparison with published high frequency PLL designs, [1,2,3,4,5]. Section 4 concludes this paper.…”