A 200μW Eight-Channel Acquisition ASIC for Ambulatory EEG Systems

Abstract

A crucial and important part of a medical diagnostics system is the monitoring of the biopotential signals. This paper describes a complete low-power EEG acquisition ASIC that is suitable for miniaturized ambulatory EEG measurement systems. The aim is not only to improve the patients' comfort but also to extend the device applications. Figure 8.2.1 shows the architecture of the EEG acquisition ASIC, which is implemented in a 0.5µm CMOS process. It consists of eight readout channels, an 11b ADC, a square-wave oscillator and a bias circuit. In addition to the acquisition mode, the ASIC has calibration and impedance measurement modes.The EEG signals are µV-range low-frequency signals that are correlated with a large amount of common-mode (CM) interference. Therefore, a low-noise and high-CMRR amplifier is necessary, for which chopping is commonly used [1]. However, the differential electrode offset (DEO) voltage between the biopotential electrodes requires filtering prior to amplification. The AC-coupled chopperstabilized instrumentation amplifiers (ACCIA) can achieve high-CMRR and eliminate 1/f noise, while filtering the DEO by using a DC servo-loop outside the choppers that introduces a high-pass filter (HPF) characteristic [2,3]. The implementation in [3] however, has a low input impedance (7.5MΩ), which is suitable for implantable applications but does not meet the expectations of regular clinical EEG systems (100MΩ) [4]. In contrast, the system described in [2] meets the requirements for clinical EEG but has worse power-noise performance than [3]. Figure 8.2.2 shows the concept and the implementation of the proposed ACCIA.The servo-loop is divided into a coarse low-pass filter (LPF) with discrete output levels and a fine LPF with a continuous output range to mimic the operation of a single servo-loop with a continuous output range. The core amplifier is a current balancing IA (CBIA) similar to [2] that is followed by a gain stage. If the current through R 1 due to the DEO can be supplied by the fine-coarse servo-loop, which consists of an integrator, a coarse transconductance (CGM) and a fine transconductance (FGM), the DEO can be filtered. Thanks to the CGM, the FGM does not need to supply all the current for the specified DEO range, which reduces its power dissipation significantly compared to [2]. The CGM uses two comparators to periodically check whether the FGM has reached its limit and to control the current DAC. However, a critical concern about the fine-coarse operation of the servo-loop is the steering of the current DAC of the CGM stage since a conventional DAC will create voltage steps at the output of the ACCIA during every DAC bit change. Therefore, the steering time-constant of the DAC must be much smaller than (1/2πf HP ) so that the FGM can suppress the artifact by adjusting its output (f HP is the HPF cut-off frequency of the ACCIA set by the fine servo-loop).Figure 8.2.3 shows the "slow-DAC" implementation. The transistors M 1 and M 2 serve as pass-gates. The output current measurement of a cu...

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