A 200-MHZ double-sideband to single-sideband converter in 1- mu m CMOS generated by silicon compiler

Strategies for design automation of high speed digital filters

“…These optimizations have already been included in several filter compilers [8] [31], but have yet to appear in general purpose DSP synthesis tools.…”

“…Figure 1 shows an 8-tap FIR filter with coefficients h0 -hT. To meet the conditions of linear phase, the tap coeffi-6) It is usually desirable to make use of the symmetry of linear phase FIRs to reduce the amount of hardware required [27] [8]. The number of multipliers can be reduced by approximately a factor of two whithout speed degradation by sharing the multipliers between symmetric taps.…”

“…As presented in [8] an improved method of implementing the anti-symmetric linear phase FIR is to negate the partial sum after the first half of the taps and negate all tap coefficients as shown in Figure 5. It is much more difficult to derive this structure using automated optimization techniques.…”

“…When the sign bit is fed into the most significant N bits of an adder, much of the circuitry of these N full adds becomes unnecessary. The effect of the sign-bit on the N -1 most significant full adds can be precomputed and reduced to constant values fed into the sum inputs [8]. Again, since one of the inputs to each full adder is known a priori, they can be replaced by half adders.…”

“…These bit-level circuit optimization techniques have been incorporated in filter compilers [8] [31] and result in both area savings and critical path minimization. While the above procedures can easily automate these optimizations, they are presently not included in any known DSP synthesis system.…”