Strategies for design automation of high speed digital filters

Abstract

Abstract. Optimization techniques for DSP circuits are described based on the design experience with a number of high-speed digital filter chips. These designs show that efficient high speed digital filter designs can be achieved using several optimizations at the architecture, circuit, and layout level. The problems of automating these optimizations in a general DSP synthesis environment are discussed, and possible CAD solutions are proposed.

Low power implementation of linear phase FIR filters for single multiplier CMOS based DSPs

“…An algorithmic outline of the multiplication scheme is given below: Using this scheme the authors showed that up to 63% reduction in switching activity could be achieved. However, the investigations carried out in [1,2] assumed , $ n r ; $ill Test Vector Generator the following: (1) the switching power is proportional to the switching activity with disregard to loading and Generalor Input parasitic capacitances, and spurious timing information such as glitches, (2) a randomly distributed pattern of inputs on both data and coefficient inputs of the multiplier, applications a phase distortion can not be tolerated and Such filters require a symmetric or anti-symmetric (about the central tap) set of coefficients [5]. In this paper the authors extend the scheme to linear phase FIR filters and show a more significant overall power reduction of up to 85% using a comprehensive simulation environment which combines layout, timing, and capacitive information.…”

“…In this paper the authors extend the scheme to linear phase FIR filters and show a more significant overall power reduction of up to 85% using a comprehensive simulation environment which combines layout, timing, and capacitive information. In addition to the transpose direct form realisation, in this work the scheme has been used with another common realisation structure for linear phase FIR filters [5], see Figure 1. This structure, commonly known as folded transpose direct form as opposed to the unfolded realisation of the transpose direct form, exploits the 2.…”