Low power implementation of linear phase FIR filters for single multiplier CMOS based DSPs

Abstract

Recently, a new scheme for the single multiplier implementation of low power digital filters on CMOSbased DSPs was presented [1,2]. In this paper the scheme is generalised to include linear phase FIR filters (LPFIRs) and its implementation is investigated with two common methods of LPFIR realisation structures. The paper also describes an effective framework which combines layout, timing, and capacitive information, for the evaluation of power consumption for FIR filters. New results are provided which demonstrate up to 85% reduction in overall power consumption. The paper discusses the generalisation of the scheme to LPFIRs and the effects of added overheads, describes the evaluation environment, and provides comprehensive results which show the effectiveness of the scheme as a generic power saving framework for the implementation of FIR filters exploiting coefficient symmetry, where exists, without the need for specialised realisation structures.

Design Methodology of FIR Filtering IP Cores for dsp based Systems

“…The filter can be implemented in Unfolded Direct Form, Folded Direct form and Transposed form. FIR filter may require many stages in order to provide a suitable response and therefore, rather than using a multiplier for each filter stage, a more economical means of realizing such a system is to use single multiplier [4].The basic input output relationship for Mth order FIR filter can be written as follows [5]. The mapping possibilities of Eq.…”

“…Most researchers have implemented FIR Filter IP Cores using parallel architectures with multiple data paths requirement (for Coefficient Segmentation algorithm and Block processing algorithm) [3].The sequential implementation needs single multiplier and is favorable in terms of cost and area performance. To minimize the overheads of design, single multiplier architecture is selected for implementation [4]. The digital filters are built by the combination of several digital building blocks such as adders, multipliers, mac, muxes and memories etc.The design of identical function with different data widths has become possible with introduction of Hardware Description Languages (HDL's) and synthesis tools.…”

A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters

“…In Refs. [9,10], we have presented techniques that utilise various folded/unfolded filter realisation structures in conjunction with coefficient ordering algorithms for minimising power consumption in FIR filters. Other techniques used by researchers include the use of multirate architectures [11,12], and dynamic adjustment of filter order for adaptive filters [13].…”