A 200 MHz 2.5 V 4 W superscalar RISC microprocessor

Abstract

This RISC microprocessor is based on a microarchitecture designed in a 2.5V CMOS technology [l]. The 78.75mm2 design features dual 16kB instruction and data caches, a floating-point unit, an integer unit, a branch unit, a loadstore unit, and a system unit. Two instructions per cycle can be dispatched in this superscalar design. The user-configurable multiplying PLL provides a processor clock at 2X, 2.5X, 3X, 3.5X, 4X, 4.5X, 5X, 5.5X, and 6X the bus clock frequency. Testability features include level-sensitive-scan-design (LSSD), array-built-in-self-test (ABIST) logic for cache and tag arrays, and a JTAG interface [21. Figure 1 is a block diagram of the processor, and Figure 2, a micrograph.

Performance improvement with circuit-level speculation

“…[14,15] superscalar processor include, register rename logic and issue logic. Also as the machine data and address width increases (currently moving from 32 to 64 bits), we believe adder may also become a bottleneck limiting the increase in frequency because many groups reporting the design of high performance microprocessors include their add circuits in their papers [16][17][18]. This suggests that adder may limit the frequency of microprocessor if we want to have finer pipeline stages in the future.…”

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

“…Furthermore, advances in device integration leads to larger chips that require the distribution of accurate clock signals. Because the distribution tree may have radically different lengths and parasitics, synchronization of the clock signals at the receivers can be difficult and has been the subject of much interest [1], [2], [9]. To date, complementary metal-oxide-semiconductor (CMOS) technology has been the dominant throughout the industry, but it has not displaced other technologies for extremely high-speed designs.…”