A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller

Gerosa, G.; Alexander, M.; Álvarez, José Marcos Alonso; Croxton, C.; D'Addeo, M.; Kennedy, A.R.; Nicoletta, C.; Nissen, Jene; Philip, R.; Reed, Paul; Sanchez, H.; Taylor, Scott A.; Burgess, B.

doi:10.1109/4.641684

Cited by 25 publications

(6 citation statements)

References 8 publications

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“…The FETA circuit is designed and tested based on the proposed hardware logic, which is illustrated in Figure 2, that has two input signals (RREQ, WREQ) with two associated output signals (RREQC, WREQC) and one external reset signal (EXTRES). The essential design component is DFF, that is, commercially listed in the PowerPC master-slave latch with the main advantages of a short, direct path and low-power feedback [12]. Although the literature is highly rich with different DFF designs that provide further key factors and advantages, this work aims to use standard library components rather than leveraging the design performance through a special DFF or special technology.…”

Section: Simulations and Resultsmentioning

confidence: 99%

A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems

Abdel‐hafeez

Harb

2023

IET Computers & Digital Tech

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In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered. In such a case, multiple overlapping signal requests can potentially compete in the same PE causing erroneous operations or a halt of the communication cycle. The authors propose a self‐timing CMOS first‐edge take‐all (FETA) circuit architecture, which examines two overlapping signals’ requests, and outputs only the leading‐edge signal while the lagging‐edge signal's request is declined. The FETA circuit functionality is considered as an essential component in First‐In‐First‐Out for metastability avoidance, which usually occurs between the write and read overlapping requests for applications related to Internet of Things, Network‐on‐Chips, and microprocessor memory management units. HSPICE simulations for a 90 nm CMOS technology are used to verify the speed up to 1 GHz. Besides, the achievable resolution is in the order of 20 ps considering process variation sensitivity based on design inheriting symmetric timing paths between the two signals. Additionally, the proposed circuit architecture adopts a self‐timing scheme obviating the overhead synchronisation circuitry, which comprises 12 D‐Type Flip‐Flops with about 300 transistors. This design is suited for HDL synthesis and FPGA application features.

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Section: Simulations and Resultsmentioning

confidence: 99%

A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems

Abdel‐hafeez

Harb

2023

IET Computers & Digital Tech

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“…Therefore high Vt devices are used to examine the accuracy of our leakage estimation methods at room temperature (temperature effects will be discussed later). A primary input activity rate of 12.5% is used, meaning that one rising and one falling event occurs every eight clock cycles which is typical of VLSI circuits [17]. Input pattern Randomly generated with activity rate of 12.5% Number of patterns 500 or 250 500 random input samples are used in the HSPICE simulations except for the larger benchmarks for which 250 cycles are simulated; large runtimes prevent running more than this.…”

Section: Simulation Setup and Resultsmentioning

confidence: 99%

Runtime leakage power estimation technique for combinational circuits

Lin¹,

Sylvester²

2007

2007 Asia and South Pacific Design Automation Conference

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This paper carefully examines subthreshold leakage during circuit operation (runtime) and develops a novel analysis technique to capture this important effect, which is currently ignored in traditional steady-state leakage calculation approaches. We implement novel dynamic and static estimation methods that provide significant speed improvements over full SPICE simulations and yield estimation errors of approximately 12% on average compared to more than 2X errors in steady-state based subthreshold leakage analysis.

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“…However, since JETTY is much smaller than the tag hierarchy it will have a small impact on overall power dissipation. Moreover, existing processors already include both temperature monitoring hardware and the mechanisms necessary (e.g., frequency or voltage scaling) to take action when appropriate [6,8].…”

Section: An Opportunity To Reduce Snoop-induced Energy Consumptionmentioning

confidence: 99%

JETTY: filtering snoops for reduced energy consumption in SMP servers

Moshovos

Memik

Falsafi

et al.

Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture

127

128

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We propose methods for reducing the energy consumed by snoop requests in snoopy bus-based symmetric multiprocessor (SMP) systems. Observing that a large fraction of snoops do not find copies in many of the other caches, we introduce JETTY, a small, cache-like structure. A JETTY is introduced in-between the bus and the L2 backside of each processor. There it filters the vast majority of snoops that would not find a locally cached copy. Energy is reduced as accesses to the much more energy demanding L2 tag arrays are decreased. No changes in the existing coherence protocol are required and no performance loss is experienced. We evaluate our method on a 4-way SMP server using a set of shared-memory applications. We demonstrate that a very small JETTY filters 74% (average) of all snoop-induced tag accesses that would miss. This results in an average energy reduction of 29% (range: 12% to 40%) measured as a fraction of the energy required by all L2 accesses (both tag and data arrays).

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A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller

Cited by 25 publications

References 8 publications

A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems

A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems

Runtime leakage power estimation technique for combinational circuits

JETTY: filtering snoops for reduced energy consumption in SMP servers

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