A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

Abstract

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time 61 modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time 61 ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The 61 ADC achieves 76-dB SNR, 78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT 61 modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply.

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

“…However, it is important to note that they have practical limitations due to noise, namely intrinsic device noise and extrinsic power supply noise. Note that noise is the fundamental reason behind even clock jitter itself (in an oscillator or a phase-locked-loop [34]) and it similarly causes variation/jitter of the feedback charge in each feedback technique (note that in typical scenarios it is assumed that the noise sources are uncorrelated so the clock jitter itself is independent from the variation/jitter of the feedback charge). In fact, any technique would only be effective to reduce clock jitter effects when the variation/jitter of the feedback charge due to noise is less or equal to that of the clock.…”

Analysis and Modeling of Clock-Jitter Effects in Delta-Sigma Modulators

“…Thus, the error generated by DAC clock PN has two main components, as illustrated by Figure 13. First, the clock PN components close to the clock frequency modulates the in-band desired signal resulting in signal side-bands in the same manner like the PN of an upfront sampler [5]. Second, the wideband clock PN, modulates the high-pass shaped noise components and the modulation products fall over the desired band and hence elevate the in-band noise level.…”

Mixed CT/DT Cascaded Sigma-Delta Modulator

“…The CT ΣΔM can be implemented using active-RC or G m -C integrators [15,16], whereas the DT ΣΔM can be realized with SC circuitry. Furthermore, in order to reduce the design complexity, one of the timeinterleaved DT ΣΔM input sampler branch can be removed.…”