A 2-GHz Highly Linear Efficient Dual-Mode BiCMOS Power Amplifier Using a Reconfigurable Matching Network

Hedayati, H.; Mobarak, Mohamed; Varin, G.; Meunier, Philippe; Gamand, P.; Sánchez-Sinencio, E.; Entesari, Kamran

doi:10.1109/jssc.2012.2203460

Cited by 18 publications

(7 citation statements)

References 26 publications

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“…Because of the low breakdown voltages for fast CMOS devices, other technologies, such as GaAs HBT [26], [27], Si bipolar [28], [29], SiGe HBT [30]- [32], and low-voltage LDMOS [33], [34], have so far dominated the small-size PAs. See [35] for CMOS vs. GaAs comparison for mobile phone PAs, and [36] for comparison of different bipolar technologies for similar applications.…”

Section: A Cmos For Wireless Socmentioning

confidence: 99%

A Review of Watt-Level CMOS RF Power Amplifiers

Johansson

Fritzin

2014

IEEE Trans. Microwave Theory Techn.

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Abstract-This paper reviews the design of watt-level integrated CMOS RF power amplifiers (PAs) and state-of-the-art results in the literature. To reach watt-level output power from a single-chip CMOS PA, two main strategies can be identified: use of high supply voltage, and use of matching and power combination. High supply voltage limits are closely related to device design in the fabrication process. However, the maximum operating voltage can be improved by amplifier class selection, circuit solutions, and process modifications or mask changes. High output power can also be reached by the use of on-chip matching and power combination, commonly using on-chip transformers. Reliability often sets the limits for the PA design, and PA degradation mechanisms are reviewed. A compilation of state-of-the-art published results for linear and switched wattlevel PAs, as well as a few fully integrated CMOS PAs, is presented and discussed.

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Section: A Cmos For Wireless Socmentioning

confidence: 99%

A Review of Watt-Level CMOS RF Power Amplifiers

Johansson

Fritzin

2014

IEEE Trans. Microwave Theory Techn.

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“…Predistortion as one of them was already applied in a high speed DAC to compensate for non-linearity of its output driver [6]. Using the main and auxiliary amplifier/driver for non-linearity cancellation [9,10] is another possible solution. As an additional inspiration the techniques developed for low noise amplifiers (LNAs) can also be considered [11][12][13][14]17].…”

Section: Output Driver Design Problem and Solutionmentioning

confidence: 99%

Design and analysis of high speed capacitive pipeline DACs

Duong

Dąbrowski

Alvandpour

2014

Analog Integr Circ Sig Process

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Abstract-Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by the capacitor mismatch or kT/C noise, which appear negligible in this application. While it is possible to design a highly linear output driver with HD3 < -70 dB and HD2 < -90 dB over 0.55 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. High linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz with Nyquist sampling. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.

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“…The Doherty technique modulates the load impedance using a quarter-wavelength transformer for both the back-off power and the peak power [6]. A reconfigurable output matching network, according to the power level, is also a good candidate for high PAPR signals [7]. However, these techniques require complex output matching networks, which have a large loss and are sensitive to a bandwidth.…”

Section: ⅰ Introductionmentioning

confidence: 99%

CMOS Linear Power Amplifier with Envelope Tracking Operation (Invited Paper)

Park¹,

Kim²,

Cho³

et al. 2014

Journal of electromagnetic engineering and science

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A differential-cascode CMOS power amplifier (PA) with a supply modulator for envelope tracking (ET) has been implemented by 0.18 μm RF CMOS technology. The loss at the output is minimized by implementing the output transformer on a FR-4 printed circuit board (PCB). The CMOS PA utilizes the 2 nd harmonic short at the input to enhance the linearity. The measurement was done by the 10 MHz bandwidth 16QAM 6.88 dB peak-to-average power ratio long-term evolution (LTE) signal at 1.85 GHz. The ET operation of the CMOS PA with the supply modulator enhances the power-added efficiency (PAE) by 2.5, to 10% over the stand-alone CMOS PA for the LTE signal. The ET PA achieves a PAE of 36.5% and an ACLRE-UTRA of -32.7 dBc at an average output power of 27 dBm.Key Words: CMOS, Envelope Tracking, Long-Term Evolution, Power Amplifier, Supply Modulator.

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A 2-GHz Highly Linear Efficient Dual-Mode BiCMOS Power Amplifier Using a Reconfigurable Matching Network

Cited by 18 publications

References 26 publications

A Review of Watt-Level CMOS RF Power Amplifiers

A Review of Watt-Level CMOS RF Power Amplifiers

Design and analysis of high speed capacitive pipeline DACs

CMOS Linear Power Amplifier with Envelope Tracking Operation (Invited Paper)

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