A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes

Zezza, Simone; Nooshabadi, Saeid; Masera, Guido

doi:10.1109/tcsi.2012.2209292

Cited by 6 publications

(8 citation statements)

References 47 publications

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Section: Implementation Area and Throughput Discussionmentioning

confidence: 99%

“…On the contrary, to the best of our knowledge, the only work addressing an implementation of the MAC decoder is [11]. However, in [11], the MAC decoder acts as MAP decoder, whereas the proposed technique relies on an ML decoder. Thus, we simplified the architecture used in [11], by removing the backward unit required to implement the BCJR algorithm.…”

Section: Implementation Area and Throughput Discussionmentioning

confidence: 99%

“…However, in [11], the MAC decoder acts as MAP decoder, whereas the proposed technique relies on an ML decoder. Thus, we simplified the architecture used in [11], by removing the backward unit required to implement the BCJR algorithm. As in [11], the MAC decoder architecture contains two AC decoders to perform 0 and 1 extension in the tree exploration, a forward unit to implement (2), two FIFOs to store the status of the AC in the explored nodes.…”

Section: Implementation Area and Throughput Discussionmentioning

confidence: 99%

“…Thus, we simplified the architecture used in [11], by removing the backward unit required to implement the BCJR algorithm. As in [11], the MAC decoder architecture contains two AC decoders to perform 0 and 1 extension in the tree exploration, a forward unit to implement (2), two FIFOs to store the status of the AC in the explored nodes. As argued in [11], since the first FIFO stores the metric obtained from 0 extension and the second FIFO the metric belonging to 1 extension, they are sorted.…”

Section: Implementation Area and Throughput Discussionmentioning

confidence: 99%

“…As in [11], the MAC decoder architecture contains two AC decoders to perform 0 and 1 extension in the tree exploration, a forward unit to implement (2), two FIFOs to store the status of the AC in the explored nodes. As argued in [11], since the first FIFO stores the metric obtained from 0 extension and the second FIFO the metric belonging to 1 extension, they are sorted. Thus, with a comparator one can compute the candidates avoiding the use of a large sorter.…”

Section: Implementation Area and Throughput Discussionmentioning

confidence: 99%

See 4 more Smart Citations

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors

Martina

Condo

Masera

et al. 2014

IEEE Embedded Syst. Lett.

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Reconfigurable embedded systems can take advantage of programmable devices, such as microprocessors and field-programmable gate arrays (FPGAs), to achieve high performance and flexibility. Support to flexibility often comes at the expense of large amounts of nonvolatile memories. Unfortunately, nonvolatile memories, such as multilevel-cell (MLC) NAND flash, exhibit a high raw bit error rate that is mitigated by employing different techniques, including error correcting codes. Recent results show that low-density-parity-check (LDPC) codes are good candidates to improve the reliability of MLC NAND flash memories especially when page size increases. This letter proposes to use a joint source/channel approach, based on a modified arithmetic code and LDPC codes, to achieve both data compression and improved system reliability. The proposed technique is then applied to the configuration data of FPGAs and experimental results show the superior performance of the proposed system with respect to state of the art. Indeed, the proposed system can achieve bit-error-rates as low as about for cell-to-cell coupling strength factors well higher than 1.0.

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Section: Implementation Area and Throughput Discussionmentioning

confidence: 99%