A 2.6 μW sub-threshold mixed-signal ECG SoC

Jocke, S. C.; Bolus, Jonathan F.; Wooters, Stuart N.; Blalock, Travis N.; Calhoun, Benton H.

doi:10.1145/1594233.1594260

Cited by 46 publications

(67 citation statements)

References 8 publications

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“…Figure 5 shows that the proposed LC successfully converts 0.4V input signal to 1.2V Figure 6 illustrates the delay simulation of the proposed design versus input signal for converting the input signal from Vin-low to Vout at 1.2V VDDH. The Proposed S_SSLC for an input signal between 0.3V-0.4V, adds less than 25 ns delay, however, these delays are appropriate for many sub-threshold applications [17][18][19]. Utilizing M7 as a diode-connected in the first stage of the proposed LC leads to a VTHn voltage drop for supply voltage of the first stage.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

A Low-Voltage Single-Supply Level Converter for Sub-VTH /Super-VTH Operation: 0. 3V to 1. 2V

Moghaddam¹,

Eshghi²,

Moaiyeri³

2013

IJCA

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Digital sub-threshold circuits are significant for ultra-low power (ULP) applications. Operating circuits at ultra-low voltage levels leads to the less power per operation. An optimized method is separating the logic blocks based on performance requirement and utilizing multiple-supply voltage (VDD) for each blocks. In order to prevent an enormous static current in these multi-VDD circuits, voltage level converters are required. The advantages of single-supply level converter (SSLC) over dual-supply level converter (DSLC) are on the grounds of pin count, congestion in supply routing, complexity and overall system cost. In this paper, a novel sub-threshold single-supply voltage level converter (S_SSLC) based on dynamically-controlled body biasing technique is presented. In this work, a dynamically-controlled body biasing is utilized for setting the threshold voltages of the transistors in order to reduce the delay. This dynamic design can convert an input signal at sub-threshold/superthreshold region ranging from 0.3v-1.2v to 1.2v as output. Simulation results at 180nm CMOS technology node demonstrate the superiority of the proposed design compared to the conventional SSLC designs.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

A Low-Voltage Single-Supply Level Converter for Sub-VTH /Super-VTH Operation: 0. 3V to 1. 2V

Moghaddam¹,

Eshghi²,

Moaiyeri³

2013

IJCA

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“…There are a few exceptions. For example, a mixed signal SoC integrating an analog front end and ADC with an 8 bit PIC processor operating in sub-threshold [25] leverages 700 nW processing to reduce the burden on the system radio (not integrated on this chip). The processor uses only 1.5 pJ/instruction at 280 mV and 450 kHz, and it can extract instantaneous R-R heart rate intervals from a raw ECG sampled at 1 kHz.…”

Section: B Hardware For Bsnsmentioning

confidence: 99%

“…Also, the processor can successfully maintain accurate computation of heart rate even when it reduces the bias currents in the input amplifier and ADC, causing those analog components to suffer in terms of their block level parameters but permitting the system to function with high fidelity. This allows the full analog front end, ADC, and digital power to drop to only 2.6 µW during heart rate extraction and raw ECG acquisition [25]. Similarly, the EEG processing node in [26] includes an analog front end, ADC, and processor for feature extraction.…”

Section: B Hardware For Bsnsmentioning

confidence: 99%

Body Sensor Networks: A Holistic Approach From Silicon to Users

et al. 2012

Self Cite

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Abstract-Body sensor networks (BSN) are emerging cyberphysical systems that promise to improve quality of life through improved healthcare, augmented sensing and actuation for the disabled, independent living for the elderly, and reduced healthcare costs. However, the physical nature of BSNs introduces new challenges. The human body is a highly dynamic physical environment that creates constantly changing demands on sensing, actuation, and quality of service. Movement between indoor and outdoor environments and physical movements constantly change the wireless channel characteristics. These dynamic application contexts can also have a dramatic impact on data and resource prioritization. Thus, BSNs must simultaneously deal with rapid changes to both top-down application requirements and bottom-up resource availability. This is made all the more challenging by the wearable nature of BSN devices, which necessitates a vanishingly small size and, therefore, extremely limited hardware resources and power budget. Current research is being performed to develop new principles and techniques for adaptive operation in highly dynamic physical environments, using miniaturized, energy-constrained devices. This paper describes a holistic cross-layer approach that addresses all aspects of the system, from low-level hardware design to higher-level communication and data fusion algorithms, to top-level applications.

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“…To this end, many sensing platforms exploit sub-V T computing. The state-of-the-art processors for sensing platforms have been reported to consume as little as a few pJ/cycle while operating in the sub-V T regime [3][4][5]. Sub-V T computing can also be applied to the CS.…”

Section: Introductionmentioning

confidence: 99%

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

Constantin

Doğan

Andersson

et al. 2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

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Abstract-Compressed sensing (CS) is a universal technique for the compression of sparse signals. CS has been widely used in sensing platforms where portable, autonomous devices have to operate for long periods of time with limited energy resources. Therefore, an ultra-low-power (ULP) CS implementation is vital for these kind of energy-limited systems. Sub-threshold (sub-VT) operation is commonly used for ULP computing, and can also be combined with CS. However, most established CS implementations can achieve either no or very limited benefit from sub-VT operation. Therefore, we propose a sub-VT application-specific instruction-set processor (ASIP), exploiting the specific operations of CS. Our results show that the proposed ASIP accomplishes 62x speed-up and 11.6x power savings with respect to an established CS implementation running on the baseline low-power processor.

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A 2.6 μW sub-threshold mixed-signal ECG SoC

Cited by 46 publications

References 8 publications

A Low-Voltage Single-Supply Level Converter for Sub-VTH /Super-VTH Operation: 0. 3V to 1. 2V

A Low-Voltage Single-Supply Level Converter for Sub-VTH /Super-VTH Operation: 0. 3V to 1. 2V

Body Sensor Networks: A Holistic Approach From Silicon to Users

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

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