TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

Constantin, Joseph; Doğan, Ahmed Yasir; Andersson, Oskar; Meinerzhagen, Pascal; Rodrigues, Joachim Neves; Atienza, David; Burg, Andreas

doi:10.1109/vlsi-soc.2012.7332094

Cited by 10 publications

(5 citation statements)

References 13 publications

(4 reference statements)

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“…• Data compression algorithm : We considered the Compress sensing (CS) algorithm [4], a 50% lossy compression algorithm used on biosignals before storing them. This application takes as input, a 3 seconds Electrocardiogram (ECG) signal and compresses it.…”

Section: Application Characterization and Simulation Methodologymentioning

confidence: 99%

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

Tuli

Rios

Levisse

et al. 2020

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

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The growing need for connected, smart and energy efficient devices requires them to provide both ultra-low standby power and relatively high computing capabilities when awoken. In this context, emerging resistive memory technologies (RRAM) appear as a promising solution as they enable cheap fine grain technology co-integration with CMOS, fast switching and non-volatile storage. However, RRAM technologies suffer from fundamental flaws such as a strong device-to-device and cycle-to-cycle variability which is worsened by aging, forcing the designers to consider worst case design conditions. In this work, we propose, for the first time, a circuit that can take advantage of recently published Write Termination (WT) circuits from both the energy and performances point of view. The proposed RRAM Variability Aware Controller (RRAM-VAC) stores and then coalesces the write requests from the processor before triggering the actual write process. By doing so, it averages the RRAM variability and enables the system to run at the memory programming time distribution mean rather than the worst case tail. We explore the design space of the proposed solution for various RRAM variability specifications, benchmark the effect of the proposed memory controller with real application memory traces and show (for the considered RRAM technology specifications) 44 % to 50 % performances improvement and from 10% to 85% energy gains depending on the application memory access patterns.

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Section: Application Characterization and Simulation Methodologymentioning

confidence: 99%

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

Tuli

Rios

Levisse

et al. 2020

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…The maximum frequency of a 4T GC is also slightly lower than that of a 3T GC because the 4T consumes larger areas, resulting in longer RBLs and, consequently, a longer read access time (RAT). 3T GC and 2T GC have approximately 20% and 35% less area than 4T GC, respectively [9].…”

Section: Proposed Cellmentioning

confidence: 98%

“…1 -layout of 45 nm Intel core i7 processor [7] Furthermore, embedded memories are one of the main consumers of power in most VLSI SoCs [8]. For instance, the power consumption of embedded memories for an ultra-low-power specific processor called TamaRISC-CS was found to be ranging from 70% to 95% of the total power [9]. In addition to this, it was found that the total dynamic and static power consumed by chips for motionless applications is up to 100w [6], while it was stated by ITRS in 2009 that for portable applications the total power consumption for the VLSI SoC processors should not exceed 0.5w or 2w for consumer processors as tablets.…”

mentioning

confidence: 99%

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Abdo¹,

Alias²,

Hamzah³

et al. 2022

IJIE

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Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-VT 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400MHz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs(others' work in K. Sharma et al.and A. Goyal et al.)the retention power of the proposed GC-eDRAM is around 80-90% lower.

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“…These expected area savings should also translate to potential energy savings from driving smaller bit-lines and wordlines. Furthermore, the static power consumption due to leakage has been estimated to contribute to more than 60% of the total power consumption in modern CMOS SRAM arrays [24], [25]. We, therefore, expect significant energy savings courtesy of the SOTFET's nonvolatility.…”

Section: B Comparison To Cmos Alternativesmentioning

confidence: 99%

Modeling and Circuit Design of Associative Memories With Spin–Orbit Torque FETs

Afuye

Guo

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This article introduces a circuits model for a proposed spin-based device called a spinorbit torque field-effect transistor (SOTFET) that can operate as a nonvolatile memory and logic device. The SOTFET utilizes an FET structure with a ferromagnetic-multiferroic (MF) gate-stack that enables read/compute and write functions to be isolated. This is achieved by a combination of a ferromagnetic layer that is programmable via spin-orbit torque coupled to an MF layer that also couples into the gate of a traditional FET. Additionally, this device has logic gate-like behavior and can be designed to operate in either AND or OR gate mode. We begin with a physics-based model of this device and derive a SPICE level model that can be integrated into the Cadence toolset. Using such a device we demonstrate MRAM, content addressable memories (CAM), and ternary CAM (TCAM) functionality with 3 to 5 transistors, a significant decrease over the CMOS alternative circuits, showing that such a device can enable low cost and compact associative memories not currently feasible with CMOS devices. INDEX TERMS Beyond CMOS, compact models, ferroelectric field-effect transistor (FeFET), logic-inmemory, multiferroics (MFs), nonvolatile memory, spin-orbit torque (SOT), spin-orbit torque field-effect transistor (SOTFET), spintronics.

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TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

Cited by 10 publications

References 13 publications

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Modeling and Circuit Design of Associative Memories With Spin–Orbit Torque FETs

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