A Low-Voltage Single-Supply Level Converter for Sub-VTH /Super-VTH Operation: 0. 3V to 1. 2V

Abstract

Digital sub-threshold circuits are significant for ultra-low power (ULP) applications. Operating circuits at ultra-low voltage levels leads to the less power per operation. An optimized method is separating the logic blocks based on performance requirement and utilizing multiple-supply voltage (VDD) for each blocks. In order to prevent an enormous static current in these multi-VDD circuits, voltage level converters are required. The advantages of single-supply level converter (SSLC) over dual-supply level converter (DSLC) are on the grounds of pin count, congestion in supply routing, complexity and overall system cost. In this paper, a novel sub-threshold single-supply voltage level converter (S_SSLC) based on dynamically-controlled body biasing technique is presented. In this work, a dynamically-controlled body biasing is utilized for setting the threshold voltages of the transistors in order to reduce the delay. This dynamic design can convert an input signal at sub-threshold/superthreshold region ranging from 0.3v-1.2v to 1.2v as output. Simulation results at 180nm CMOS technology node demonstrate the superiority of the proposed design compared to the conventional SSLC designs.

An Energy-Efficient and Robust Voltage Level Converter for Nanoelectronics

“…This section examines the proposed SSLC as well as the previous LC designs [13][14][15][16] based on the comprehensive MOSFET-like CNTFET SPICE model provided by Stanford University [8] at 32nm technology node. In order to make a fair comparison all of the previous designs are also optimized using the CNTFET technology.…”

“…The SSLC design demonstrated in Fig.2(d) [16] utilizes static body-biasing for input n-type transistors to reduce the power consumption. However, this dictates the requirement for separated bodies for these transistors to avoid latch-up problem which destroy the reliability.…”

Ultra low-power 7T SRAM cell design based on CMOS

“…As a result, during the hold state RWL is changed to VDD, with this assumption that the node Q voltage is high, the VDS of M7 becomes zero which suppresses the DIBL and consequently increases the threshold voltage of M7 according to (1). In addition, as in this situation the voltages of source and body nodes of M7 are high (VBS = 0), the threshold voltage of M7 increased even more according to (1). As a result, the power consumption and leakage current of the readout path are reduced significantly.…”

“…Low-power design as significant challenge in energylimited applications comprise different levels such as, logic, circuit, device and system [1][2][3].…”