A 2.5GHz 32nm 0.35mm² 3.5dB NF &#x2212;5dBm P<inf>1dB</inf> fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection

Abstract

Intel, Hillsboro, ORProcess scaling enables SoC integration of radio and large digital systems at reduced cost and area. Furthermore, the crowded spectrum requires high linearity receivers to enable co-existence in the 2.4GHz ISM band. Inductorless LNA designs have been studied to make use of the excess f T in advanced CMOS technologies to lower cost [1]. However, an inductively tuned LNA has the advantage of improved out-of-band rejection, and can be readily integrated with a transmit/receive (T/R) switch to provide isolation in the TX mode without the need for additional inductors [2]. In this paper, a 2.5GHz fully differential tuned LNA with integrated T/R switch is designed in a High-K metal gate 32nm digital CMOS process, and packaged in an SoC-compatible flip-chip package. Reliability constraints of the package severely limit the ability to depopulate soldering bumps, and RF components must be designed taking the bump location into account. The LNA achieves a 3.5dB NF, -5dBm P 1dB at 2.5GHz while drawing 11mA from a 1.8V supply. LNA performance is enabled by (1) use of a push-pull topology that exploits the equal strength of p and n transistors to improve linearity, (2) use of nested coupled inductors (NCI) for low-noise input matching and to reduce area. The T/R switch handles 34dBm of power with an insertion loss of 1.1dB at 2.5GHz. T/R switch performance is enabled by (1) reuse of LNA gate inductor to enable low RX mode loss [2], (2) use of remote body-contacted TX switch with high power handling and ESD protection for a transformercoupled PA. Figure 3.3.1 shows the block diagram of the LNA and integrated T/R switch.The TX switch consists of a minimum gate length NMOS transistor with a remote body contact. The RX switch is combined with the input matching network of the LNA and contributes negligible loss to the RX NF. The RF I/O has 50ohm differential impedance, which is transformed to single-ended 50ohm using an off-chip balun. Figure 3.3.2 illustrates the combination of PMOS and NMOS sourceinductive-degenerated LNA stacked to create the push-pull LNA. The similar performance of the p and n transistors in the 32nm hi-K metal gate process [3] improves the push-pull LNA to achieve a good NF, and allows for similar-valued source-degeneration inductors, which is important for area reduction. The pushpull topology improves the linearity by combining the complementary response of the gm non-linearity for the p and n transistors to obtain a constant transconductance with changes in input voltage [4]. Additionally, the effective AC gain to the p and n gates from the input, and the design among cascode transistors and load resistance affect the linearity. The schematic of the fully differential LNA with the Rx switch is illustrated in Fig. 3.3.3. Bias of the p and n transistors is generated by a replica bias circuit and is optimized for maximum linearity. The gate voltage is chosen to maximize output swing while maintaining sufficient f T . Thin-gate devices with the minimum channel length are chosen to maximum...

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“…Within the scope of his teaching and research activities, he has taught 21 bachelor and master courses and, in UM, has supervised (or cosupervised) 46 theses, Ph.D. (25) and masters (21). He has coauthored seven books and 11 book chapters; 33 patents, USA (30)…”

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