A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM

Lee, T.H.; Donnelly, Kevin; Ho, J.; Zerbe, J.; Johnson, M.; Ishikawa, Takashi

doi:10.1109/isscc.1994.344632

Cited by 7 publications

(7 citation statements)

References 2 publications

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“…The octaphase clocks from the PLL are applied to the voltage-controlled delay line (VCDL) whose delay is controlled by the CDR loop to locate the edges of the octaphase clocks at the center of the received-data window. For correct operation of the 1/8-rate linear PD, the duty cycles of the VCDL outputs are adjusted to be 50% by the analog duty-cycle corrector [8].…”

Section: Architecture Of Cdrmentioning

confidence: 99%

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

Seo

Lee

Kim

et al. 2009

IEEE Trans. Circuits Syst. II

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With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-m CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the design of circuits such as the PD and charge becomes much easier, and the maximum data rate is no longer limited by the speed of phase detection. The CDR shows 6.8-ps rms and 57.4-ps peak-to-peak jitter in the recovered clock and 10 12 bit error rate for 2 31 1 pseudorandom binary-sequence input while consuming 144 mW from a 1.8-V supply.Index Terms-Clock and data recovery (CDR) , CMOS, subrate linear phase detector (PD).

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Section: Architecture Of Cdrmentioning

confidence: 99%

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

Seo

Lee

Kim

et al. 2009

IEEE Trans. Circuits Syst. II

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“…A DLL relying on quadrature phase mixing [3] has been proposed to overcome the limited range problem of the conventional DLL. The phase mixing technique using quadrature clocks provides unlimited phase shift capability.…”

Section: (B)mentioning

confidence: 99%

“…(2) The sensitivity of over to process variations should be analyzed to guarantee a reliable operation. For example, the sensitivity to the threshold voltage variation of the transistor can be obtained by (3), shown at the bottom of the page. In (3), means of transistor .…”

Section: A Low-jitter Schemementioning

confidence: 99%

A dual-loop delay-locked loop using multiple voltage-controlled delay lines

Jung

Lee

Shim

et al. 2001

IEEE J. Solid-State Circuits

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This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty cycle corrector immune to prevalent process mismatches. A test chip has been fabricated using a 0.25-m CMOS process. At 400 MHz, the peak-to-peak jitter with a quiet 2.5-V supply is 54 ps, and the supply-noise sensitivity is 0.32 ps/mV.

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“…Practically this is challenging, as the current produced by a current source as shown in Another way to realize variable delay is by phase interpolation, which can be implemented using current sources [18][19], resistors [20][21] or delay lines [22]. The basic concept of interpolation and example waveforms are shown in Fig.…”

Section: Introductionmentioning

confidence: 99%