With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-m CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the design of circuits such as the PD and charge becomes much easier, and the maximum data rate is no longer limited by the speed of phase detection. The CDR shows 6.8-ps rms and 57.4-ps peak-to-peak jitter in the recovered clock and 10 12 bit error rate for 2 31 1 pseudorandom binary-sequence input while consuming 144 mW from a 1.8-V supply.Index Terms-Clock and data recovery (CDR) , CMOS, subrate linear phase detector (PD).
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