25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

Lee, Dong Uk; Kim, Kyung Whan; Kim, Kwan Weon; Kim, Hongjung; Kim, Ju Young; Park, Young Jun; Kim, Jaehwan; Kim, Dae Suk; Park, Heat Bit; Shin, Jong-Yeol; Cho, Jang Hwan; Kwon, Ki Hun; Kim, Min Jeong; Lee, Jaejin; Park, Kun Woo; Chung, Byong-Tae; Hong, Seongin

doi:10.1109/isscc.2014.6757501

Cited by 153 publications

(65 citation statements)

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“…For example, Intel's 72-core Knights Landing processor will include up to 16GB in-package DRAM, backed by up to 384GB offpackage DDR4 DRAM. AMD [1], IBM [19], and Sony [4] also plan to adopt die-stacked High Bandwidth Memory (HBM) [24] for their future processor SoCs.…”

Section: Introductionmentioning

confidence: 99%

A fully associative, tagless DRAM cache

Lee

Kim

Jang

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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This paper introduces a tagless cache architecture for large in-package DRAM caches. The conventional die-stacked DRAM cache has both a TLB and a cache tag array, which are responsible for virtual-to-physical and physical-to-cache address translation, respectively. We propose to align the granularity of caching with OS page size and take a unified approach to address translation and cache tag management. To this end, we introduce cache-map TLB (cTLB), which stores virtual-to-cache, instead of virtual-to-physical, address mappings. At a TLB miss, the TLB miss handler allocates the requested block into the cache if it is not cached yet, and updates both the page table and cTLB with the virtual-tocache address mapping. Assuming the availability of large in-package DRAM caches, this ensures that an access to the memory region within the TLB reach always hits in the cache with low hit latency since a TLB access immediately returns the exact location of the requested block in the cache, hence saving a tag-checking operation. The remaining cache space is used as victim cache for memory pages that are recently evicted from cTLB. By completely eliminating data structures for cache tag management, from either on-die SRAM or inpackage DRAM, the proposed DRAM cache achieves best scalability and hit latency, while maintaining high hit rate of a fully associative cache. Our evaluation with 3D ThroughSilicon Via (TSV)-based in-package DRAM demonstrates that the proposed cache improves the IPC and energy efficiency by 30.9% and 39.5%, respectively, compared to the baseline with no DRAM cache. These numbers translate to 4.3% and 23.8% improvements over an impractical SRAM-tag cache requiring megabytes of on-die SRAM storage, due to low hit latency and zero energy waste for cache tags.

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Section: Introductionmentioning

confidence: 99%

A fully associative, tagless DRAM cache

Lee

Kim

Jang

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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“…Hash experiences limited throughput gains (10%) from HBM, mostly due to its sequential-access partitioning phase. Sort's advantage over Hash is likely to grow as HBM's bandwidth continues to scale [38]. (4) HBM favors sequential-access algorithms even though they incur higher algorithmic complexity.…”

Section: Exploiting Hbmmentioning

confidence: 99%

StreamBox-HBM

Miao¹,

Jeon²,

Pekhimenko³

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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Stream analytics has an insatiable demand for memory and performance. Emerging hybrid memories combine commodity DDR4 DRAM with 3D-stacked High Bandwidth Memory (HBM) DRAM to meet such demands. However, achieving this promise is challenging because (1) HBM is capacitylimited and (2) HBM boosts performance best for sequential access and high parallelism workloads. At first glance, stream analytics appears a particularly poor match for HBM because they have high capacity demands and data grouping operations, their most demanding computations, use random access.This paper presents the design and implementation of StreamBox-HBM, a stream analytics engine that exploits hybrid memories to achieve scalable high performance.StreamBox-HBM performs data grouping with sequential access sorting algorithms in HBM, in contrast to random access hashing algorithms commonly used in DRAM. StreamBox-HBM solely uses HBM to store Key Pointer Array (KPA) data structures that contain only partial records (keys and pointers to full records) for grouping operations. It dynamically creates and manages prodigious data and pipeline parallelism, choosing when to allocate KPAs in HBM. It dynamically optimizes for both the high bandwidth and limited capacity of HBM, and the limited bandwidth and high capacity of standard DRAM.StreamBox-HBM achieves 110 million records per second and 238 GB/s memory bandwidth while effectively utilizing all 64 cores of Intel's Knights Landing, a commercial server with hybrid memory. It outperforms stream engines with sequential access algorithms without KPAs by 7× and stream engines with random access algorithms by an order Permission to make digital of magnitude in throughput. To the best of our knowledge, StreamBox-HBM is the first stream engine optimized for hybrid memories.

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“…A controller chip is stacked in HMC and failure bits and failure TSVs can be repaired by the controller chip. The 3D DRAM called HBM (High Bandwidth Memory) is also fabricated for high-end systems [33]. A cost/performance ratio is significantly improved in HMC and HBM since an extremely wide bandwidth can be achieved.…”

Section: D-stacked Memoriesmentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

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25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

Cited by 153 publications

References 1 publication

A fully associative, tagless DRAM cache

A fully associative, tagless DRAM cache

StreamBox-HBM

Recent progress in 3D integration technology

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