A dual-loop delay-locked loop using multiple voltage-controlled delay lines

Jung, Yeon Jae; Lee, Seung-Wook; Shim, Dongha; Kim, Wonchan; Kim, Changhyun; Cho, Soo-In

doi:10.1109/4.918916

Cited by 68 publications

(4 citation statements)

References 9 publications

(11 reference statements)

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“…For example, a technique employing a Digital-to-Analog Converter (DAC) with Parallel Variable Resistor (PVR) is used to realize high-resolution delay steps with a wide delay range by accurately controlling the Current-Controlled Delay Element (CCDE) of the DLL [1]. Another technique developed is the use of a dual-loop architecture which utilizes multiple delay lines [6]. The first “reference” loop generates a clock with quadrature phases.…”

Section: Introductionmentioning

confidence: 99%

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

Abdulrazzaq

Ibrahim

Kawahito

et al. 2016

Sensors

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A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL’s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture’s circuit is 0.1 mW when the DLL is operated at 2 GHz.

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Section: Introductionmentioning

confidence: 99%

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

Abdulrazzaq

Ibrahim

Kawahito

et al. 2016

Sensors

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“…Lock range indicates the maximum and minimum delays of the VCDL and directly affects the DLL’s operating frequency range (Jia 2005 ). Lock range can be increased by including more delay elements in the VCDL, for example (Yeon-Jae et al 2001 ; Yang 2003 ). The locking time refers to the time required for a DLL to reach a stable locking state from an initial state.…”

Section: Analog-tunable Delay Elementsmentioning

confidence: 99%

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

et al. 2016

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A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

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“…A number of methods are presented in the literatures for designing DLL. A number of these methods involve the design of a wide range DLL to solve the problem of false locking [7][8][9][10]. In [8], an all-analog DLL is introduced that utilizes a replica delay line to solve the problem of narrow frequency range.…”

Section: Introductionmentioning

confidence: 99%

“…DLL is provided with dual loop architectures in which the delay range is improved by utilizing the technique of multiple voltage-controlled delay lines. The architecture of this DLL is usually complex, as a result the area and power consumption increase and the performance of the jitter deteriorates [9]. In [11], a dual loop DLL structure with linear delay elements is presented.…”

Section: Introductionmentioning

confidence: 99%

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

Saraji,

Ghorbani,

Anisheh

2023

Analog Integr Circ Sig Process

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Delay lock loop (DLL) is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques which has a good current matching. The delay cell uses the bulk-driven technique and has less power consumption than conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 μm CMOS process with the supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure.

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A dual-loop delay-locked loop using multiple voltage-controlled delay lines

Cited by 68 publications

References 9 publications

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

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