A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications

Abstract

This brief presents a fast Fourier transform (FFT) processor that provides high throughput rate (T.R.) by applying the eight-data-path pipelined approach for wireless personal area network applications. The hardware costs, including the power consumption and area, increase due to multiple data paths and increased wordlength along stages. To resolve these issues, a novel simplification method to reduce the hardware cost in multiplication units of the multiple-path FFT approach is proposed. A multidata scaling scheme to reduce wordlengths while preserving the signal-to-quantization-noise ratio is also presented. Using UMC 90-nm 1P9M technology, a 2048-point FFT processor test chip has been designed, and its 128-point FFT kernel has been fabricated for ultrawideband (UWB) applications and also for verification. The 2048-point FFT processor can provide a T.R. of 2.4 GS/s at 300 MHz with a power consumption of 159 mW. Compared with the four-data-path approach, a power consumption saving of about 30% can be achieved under the same T.R. In addition, the 128-point FFT kernel test chip has a measured power consumption of 6.8 mW with a T.R. of 409.6 MS/s at 52 MHz to meet the UWB standard with a saving in power consumption of about 40%. Index Terms-Dynamic scaling, fast Fourier transform (FFT), orthogonal frequency-division multiplexing (OFDM), ultrawideband (UWB), wireless personal area network (WPAN).

Area-Efficient FFT Kernel with Improved Use of GI for Multistandard MIMO-OFDM Applications

“…An SDF 128-point FFT processor was developed based on the radix-2 4 algorithm [30] and its performance was extended to four streams for evaluation. That which is compared deals with devices based on different technologies; therefore, the area was normalized [Equation (8)] based on the scheme in [27,33]. Although the GI duration is relatively short (e.g., 1/4 symbol duration) in timeliness considerations, the proposed FFT kernel could lend support to a throughput gain of (6/4) for the number of streams, only mainly needing additional memory elements for the two-stream data storage.…”

VLSI design of low‐cost and high‐precision fixed‐point reconfigurable FFT processors

“…The memorybased architecture [3][4][5] provides a low-power solution; however, this approach suffers from long latency and may require additional buffer space for system synchronisation. The pipelined architecture including single-path delay feedback (SDF) pipeline FFT architecture [1,6] and multipath delay commutator (MDC) architecture [7][8][9], provides high throughputs, but it requires more hardware resources at the same time.…”