Area-Efficient FFT Kernel with Improved Use of GI for Multistandard MIMO-OFDM Applications

Tang, Song-Nien; Chen, Yuan-Ho

doi:10.3390/app9142877

Cited by 3 publications

(4 citation statements)

References 29 publications

(96 reference statements)

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“…B_LSD_RS algorithm scans the integer sequence from low bit to high bit. [37][38][39][40][41][42] Starting with the 0th bit, compare the 0th bits of all elements in the integer sequence number, move the element with the value 0 forward, and move the element with the value 1 back. Because the most bit number TA B L E 1 Sequential B_LSD_RS of eight elements of elements in the integer sequence is m, the algorithm needs to loop m times.…”

Section: Principle Of Algorithmmentioning

confidence: 99%

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A radix sorting parallel algorithm suitable for graphic processing unit computing

Xiao

Guo

et al. 2020

Concurrency and Computation

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Radix sorting is an essential basic data processing operation in many computer fields. It has important practical significance to accelerate its performance through Graphic Processing Unit (GPU). The heterogeneous parallel computing technology attracts much attention and is widely applied for its effective computation efficiency and parallel real-time data processing capability. Taking advantage of the parallelism of GPU in numerical computation processing, a parallelization design method of the Binary_Least Significant Digit (LSD) first Radix Sorting (B_LSD_RS) algorithm based on Open Computing Language (OpenCL) is proposed. The radix sorting algorithm is divided into multiple kernel tasks, and the kernels are sequentially controlled by the event information transfer. The parallel algorithm is implemented and verified on the GPU + CPU heterogeneous platform. The experimental results show that compared with the performance of the B_LSD_RS sequential algorithm based on AMD Ryzen5 1600X CPU, B_LSD_RS parallel algorithm based on Open Multi-Processing (OpenMP) and B_LSD_RS parallel algorithm based on Compute Unified Device Architecture (CUDA), the B_LSD_RS parallel algorithm based on OpenCL obtained 28.86 times, 11.01 times and 2.14 times speedup in the NVIDIA GTX 1070 computing platform respectively, not only achieves high performance but also achieves performance portability among different GPU computing platforms.

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Section: Principle Of Algorithmmentioning

confidence: 99%

“…B_LSD_RS algorithm scans the integer sequence from low bit to high bit 37‐42 . Starting with the 0th bit, compare the 0th bits of all elements in the integer sequence number , move the element with the value 0 forward, and move the element with the value 1 back.…”

Section: Computational Characteristics Analysis Of Radix Sorting Algomentioning

confidence: 99%

A radix sorting parallel algorithm suitable for graphic processing unit computing

Xiao

Guo

et al. 2020

Concurrency and Computation

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“…The mechanism and implications of boundary effects can be drawn from these parametric studies. S. N. Tang et al [7] reported on "Area-efficient FFT Kernel with Improved Use of GI for Multistandard MIMO-OFDM Applications". This study presents a fast Fourier transform (FFT) kernel for multistandard applications, which employ multiple-input, multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM).…”

Section: Topics Of Selected Papersmentioning

confidence: 99%

Special Issue: Selected Papers from IEEE ICASI 2019

et al. 2020

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“…The zero-padded FFT offers increased frequency resolution by extending the length of the input data sequence in the time domain by padding with zeros at the tail of the discrete-time signal. Because of this, it has been widely used for wireless communications and radar systems that require high-frequency resolution [4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

et al. 2019

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This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2 2 and the radix-2 3 single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most complex units and that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded and that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can dramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors were designed using hardware description language (HDL) and were synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 40,396, which can be efficient and suitable for zero-padded FFT processors.

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Area-Efficient FFT Kernel with Improved Use of GI for Multistandard MIMO-OFDM Applications

Cited by 3 publications

References 29 publications

A radix sorting parallel algorithm suitable for graphic processing unit computing

A radix sorting parallel algorithm suitable for graphic processing unit computing

Special Issue: Selected Papers from IEEE ICASI 2019

Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

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