A 2.4‐GHz frequency synthesizer with a discrete‐time sample‐hold‐reset loops filter

Abstract

A 2.4‐GHz integer‐N frequency synthesizer is implemented in TSMC 0.18‐μm CMOS process. This article proposes a charge pump (CP) linearization technique and uses a current‐switching differential Colpitts VCO to lower the phase noise and an averaged varactor circuit to increase the linearity of the VCO tuning range. A three phase sample‐hold‐reset loop filter that isolates the CP output node from the VCO tuning node, which improves synthesizer spur performance, minimizes phase noise and reduces on‐chip capacitors area. At 1.8 V supply voltage, measured results of the proposed prototype achieves a wide tuning range from 2.24 to 2.42 GHz, corresponding to 7.7%, a phase noise of −114.76 dBc/Hz at 1 MHz offset frequency from 2.4 GHz, a power consumption of 13.6 mW and an output power of −8.43 dBm. Including pads, the chip area only occupies 0.849 (0.899 × 0.944) mm2. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2591–2598, 2014