Fractional-N Frequency Synthesizer with Low Phase Noise and Low Power Dissipation for Intelligent Vehicle-to-Vehicle Radio Control Applications

Lai, Wen‐Cheng

doi:10.1109/cacs50047.2020.9289719

Cited by 1 publication

(1 citation statement)

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“…Both [ 17 , 20 ] achieve wide tuning range, lower consumption power, but also using advanced process and obtaining bad phase noise. Literature [ 21 ] consumes high power consumption, low phase noise, and output frequency same as proposed article. Literature [ 22 ] consumes low power consumption, low phase noise, but output frequency lower than proposed paper.…”

Section: Experiments and Discussionmentioning

confidence: 99%

Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing

Lai

2022

Sensors

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5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not only optimized the chip dimensions, but also precludes the influence of process shrinks and has the advantage of noise immunity. The elements of novelties of this article are low phase noise and low power consumption. With 1.8 V supply voltage and locking at 5.22 GHz, measured results find that the output signal power is −8.03 dBm, the phase noise is −110.74 dBc/Hz at 1 MHz offset frequency and the power dissipation is 16.2 mW, while the die dimensions are 0.901 × 0.935 mm2.

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Section: Experiments and Discussionmentioning

confidence: 99%